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ELOG, soc/intel: Avoid some preprocessor use 

Change-Id: I5378573f37daa4f09db332023027deda677c7aeb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-11-06 12:07:05 +02:00 committed by Patrick Georgi
parent c86fc8e63d
commit 056fbe49ff
7 changed files with 6 additions and 25 deletions
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4
src/soc/intel/baytrail/include/soc/pmc.h
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@ -281,11 +281,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
#if CONFIG(ELOG)
void southcluster_log_state(void);
#else
static inline void southcluster_log_state(void) {}
#endif
/* Return non-zero when RTC failure happened. */
int rtc_failure(void);

3
src/soc/intel/baytrail/smm.c
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@ -38,7 +38,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
southcluster_log_state();
if (CONFIG(ELOG))
southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());

4
src/soc/intel/braswell/include/soc/pm.h
View File

@ -242,11 +242,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
#if CONFIG(ELOG)
void southcluster_log_state(void);
#else
static inline void southcluster_log_state(void) {}
#endif
/* Return non-zero when RTC failure happened. */
int rtc_failure(void);

3
src/soc/intel/braswell/smm.c
View File

@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
southcluster_log_state();
if (CONFIG(ELOG))
southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());

10
src/soc/intel/denverton_ns/include/soc/pmc.h
View File

@ -262,14 +262,4 @@
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#if CONFIG(ELOG)
void southcluster_log_state(void);
#else
static inline void southcluster_log_state(void) {}
#endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _DENVERTON_NS_PMC_H_ */

4
src/soc/intel/fsp_baytrail/include/soc/pmc.h
View File

@ -285,11 +285,7 @@ void disable_all_gpe(void);
uint32_t chipset_prev_sleep_state(uint32_t clear);
#if CONFIG(ELOG)
void southcluster_log_state(void);
#else
static inline void southcluster_log_state(void) {}
#endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */

3
src/soc/intel/fsp_baytrail/smm.c
View File

@ -40,7 +40,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
southcluster_log_state();
if (CONFIG(ELOG))
southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());