ELOG, soc/intel: Avoid some preprocessor use

Change-Id: I5378573f37daa4f09db332023027deda677c7aeb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/baytrail/include/soc/pmc.h

@@ -281,11 +281,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if CONFIG(ELOG)
 void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
 
 /* Return non-zero when RTC failure happened. */
 int rtc_failure(void);

src/soc/intel/baytrail/smm.c

@@ -38,7 +38,8 @@ void smm_southbridge_clear_state(void)
 	uint32_t smi_en;
 
 	/* Log events from chipset before clearing */
-	southcluster_log_state();
+	if (CONFIG(ELOG))
+		southcluster_log_state();
 
 	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
 	printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());

src/soc/intel/braswell/include/soc/pm.h

@@ -242,11 +242,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if CONFIG(ELOG)
 void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
 
 /* Return non-zero when RTC failure happened. */
 int rtc_failure(void);

src/soc/intel/braswell/smm.c

@@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void)
 	uint32_t smi_en;
 
 	/* Log events from chipset before clearing */
-	southcluster_log_state();
+	if (CONFIG(ELOG))
+		southcluster_log_state();
 
 	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
 	printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());

src/soc/intel/denverton_ns/include/soc/pmc.h

@@ -262,14 +262,4 @@
 #define RST_CPU (1 << 2)
 #define SYS_RST (1 << 1)
 
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
-
-#if CONFIG(ELOG)
-void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
-
-#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
-
 #endif /* _DENVERTON_NS_PMC_H_ */

src/soc/intel/fsp_baytrail/include/soc/pmc.h

@@ -285,11 +285,7 @@ void disable_all_gpe(void);
 
 uint32_t chipset_prev_sleep_state(uint32_t clear);
 
-#if CONFIG(ELOG)
 void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
 
 #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
 

src/soc/intel/fsp_baytrail/smm.c

@@ -40,7 +40,8 @@ void smm_southbridge_clear_state(void)
 	uint32_t smi_en;
 
 	/* Log events from chipset before clearing */
-	southcluster_log_state();
+	if (CONFIG(ELOG))
+		southcluster_log_state();
 
 	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
 	printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());