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This is an otherwise dead platform. I'm just committing the basics that 

let it build. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2009-09-15 23:38:27 +00:00
parent b261205f5e
commit 057712a3b7
5 changed files with 56 additions and 50 deletions
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4
src/mainboard/dell/s1850/Config.lb
View File

@ -138,8 +138,8 @@ chip northbridge/intel/e7520 # mch
device pci 1f.2 on end
device pci 1f.3 on end
register "pirq_a_d" = "0x8a07030b"
register "pirq_e_h" = "0x85808080"
register "pirq_a_d" = "0x8e8b8f80"
register "pirq_e_h" = "0x80808080"
end
device pci 00.0 on end
device pci 00.1 on end

2
src/mainboard/dell/s1850/Options.lb
View File

@ -84,7 +84,7 @@ default CONFIG_HAVE_HARD_RESET=1
## Build code to export a programmable irq routing table
##
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=16
default CONFIG_IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table

10
src/mainboard/dell/s1850/auto.c
View File

@ -123,13 +123,13 @@ static void main(unsigned long bist)
#if 0
display_cpuid_update_microcode();
#endif
#if 0
#if 1
print_pci_devices();
#endif
#if 1
enable_smbus();
#endif
#if 0
#if 1
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
@ -141,15 +141,15 @@ static void main(unsigned long bist)
mainboard_set_e7520_leds();
// memreset_setup();
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
#if 1
dump_pci_devices();
#endif
#if 0
#if 1
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
#if 0 // temporarily disabled
#if 1 // temporarily disabled
/* Check the first 1M */
// ram_check(0x00000000, 0x000100000);
// ram_check(0x00000000, 0x000a0000);

69
src/mainboard/dell/s1850/irq_tables.c
View File

@ -1,43 +1,49 @@
/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
/*
* This file is part of the coreboot project.
*
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*17, /* there can be total 17 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x24d0, /* Device */
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * 9,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x11 << 3) | 0x0, /* Interrupt router device */
0xc20, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
0x66, /* Checksum */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
{0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
{0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
{0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
{0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
{0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
{0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
}
};
@ -45,4 +51,3 @@ unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

17
targets/dell/s1850/Config.lb
View File

@ -5,13 +5,13 @@ option CONFIG_ROM_SIZE=1024*1024
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
romimage "normal"
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x16000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../../payloads/filo.elf
payload /tmp/filo.elf
end
#romimage "normal"
# option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x16000
# option COREBOOT_EXTRA_VERSION=".0Normal"
## payload ../../../payloads/filo.elf
# payload /tmp/filo.elf
#end
romimage "fallback"
option CONFIG_USE_FALLBACK_IMAGE=1
@ -21,4 +21,5 @@ romimage "fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"