Following patch adds support for Asus M2V-E SE. Works pretty well, the only
problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers recently released, maybe with OpenChrome too. It wont work with the little patch which will hop in soon Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
parent
80d7c85fb9
commit
05839975bf
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 AMD
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## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
|
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_PAYLOAD = 1
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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##WARNING enable caching of whole ROM during CAR
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default XIP_ROM_SIZE = ROM_SIZE
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default XIP_ROM_BASE = 0xffffffff + 1 - XIP_ROM_SIZE
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arch i386 end
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driver mainboard.o
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if HAVE_ACPI_TABLES
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object acpi_tables.o
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object fadt.o
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makerule dsdt.c
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depends "$(MAINBOARD)/dsdt.asl"
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action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
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action "mv dsdt.hex dsdt.c"
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end
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object ./dsdt.o
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end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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# object reset.o
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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end
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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mainboardinit southbridge/via/k8t890/romstrap.inc
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ldscript /southbridge/via/k8t890/romstrap.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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if CONFIG_CHIP_NAME
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config chip.h
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_AM2 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # Northbridge
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/via/vt8237r # Southbridge
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register "ide0_enable" = "1" # Enable IDE channel 0
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register "ide1_enable" = "1" # Enable IDE channel 1
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register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
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register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
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register "fn_ctrl_lo" = "0xc0" # Enable SB functions
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register "fn_ctrl_hi" = "0x1d" # Enable SB functions
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device pci 0.0 on end # HT
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device pci f.1 on end # IDE
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device pci 11.0 on # LPC
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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chip superio/ite/it8712f # Super I/O
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Environment controller
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 0x00
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end
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device pnp 2e.5 off end # PS/2 keyboard
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device pnp 2e.6 off end # PS/2 mouse
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device pnp 2e.7 off end # GPIO config
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device pnp 2e.8 off end # Midi port
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device pnp 2e.9 off end # Game port
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device pnp 2e.a off end # IR
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end
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end
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device pci 12.0 on end # VIA LAN
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device pci 13.0 on end # br
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device pci 13.1 on end # br2 need to have it here to discover it
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end
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chip southbridge/via/k8t890 # "Southbridge" K8M890
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end
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end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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@ -0,0 +1,168 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License v2 as published by
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## the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_MAX_PHYSICAL_CPUS
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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# uses USE_OPTION_TABLE
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# uses CONFIG_LB_MEM_TOPK
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uses HAVE_ACPI_TABLES
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses COREBOOT_EXTRA_VERSION
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uses _RAMBASE
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uses CONFIG_GDB_STUB
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CONFIG_CHIP_NAME
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
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uses K8_HT_FREQ_1G_SUPPORT
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses DCACHE_RAM_GLOBAL_VAR_SIZE
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uses CONFIG_USE_INIT
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uses ENABLE_APIC_EXT_ID
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uses APIC_ID_OFFSET
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uses LIFT_BSP_APIC_ID
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uses HT_CHAIN_UNITID_BASE
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uses HT_CHAIN_END_UNITID_BASE
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# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
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uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
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# bx_b005+
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uses SB_HT_CHAIN_ON_BUS0
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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default ROM_SIZE = 512 * 1024
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default FALLBACK_SIZE = 256 * 1024
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default HAVE_FALLBACK_BOOT = 1
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default HAVE_HARD_RESET = 0
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default HAVE_PIRQ_TABLE = 0
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default IRQ_SLOT_COUNT = 11 # FIXME?
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default HAVE_MP_TABLE = 1
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default HAVE_OPTION_TABLE = 0 # FIXME
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# Move the default coreboot CMOS range off of AMD RTC registers.
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default LB_CKS_RANGE_START = 49
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default LB_CKS_RANGE_END = 122
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default LB_CKS_LOC = 123
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default CONFIG_SMP = 1
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default CONFIG_MAX_CPUS = 2
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default CONFIG_MAX_PHYSICAL_CPUS = 1
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default CONFIG_LOGICAL_CPUS = 1
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default HAVE_ACPI_TABLES = 1
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# default CONFIG_CHIP_NAME = 1
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# 1G memory hole
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# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
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# Opteron K8 1G HT support
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default K8_HT_FREQ_1G_SUPPORT = 1
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# HT Unit ID offset, default is 1, the typical one.
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default HT_CHAIN_UNITID_BASE = 0x0
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# Real SB Unit ID, default is 0x20, mean don't touch it at last.
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# default HT_CHAIN_END_UNITID_BASE = 0x0
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# Make the SB HT chain on bus 0, default is not (0).
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# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
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# bx_b005+ make the SB HT chain on bus 0.
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default SB_HT_CHAIN_ON_BUS0 = 1
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# Only offset for SB chain?, default is yes(1).
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default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
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default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
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default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA.
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default USE_DCACHE_RAM = 1
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default DCACHE_RAM_BASE = 0xcc000
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default DCACHE_RAM_SIZE = 0x4000
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default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
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default CONFIG_USE_INIT = 0
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default ENABLE_APIC_EXT_ID = 0
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default APIC_ID_OFFSET = 0x10
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default LIFT_BSP_APIC_ID = 0
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default CONFIG_IOAPIC = 1
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default MAINBOARD_VENDOR = "ASUS"
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default MAINBOARD_PART_NUMBER = "M2V-MX SE"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
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# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
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default ROM_IMAGE_SIZE = 64 * 1024
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default STACK_SIZE = 8 * 1024
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default HEAP_SIZE = 256 * 1024
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# More 1M for pgtbl.
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# default CONFIG_LB_MEM_TOPK = 2048
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default _RAMBASE = 0x00004000
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# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default CONFIG_ROM_PAYLOAD = 1
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default CC = "$(CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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default CONFIG_GDB_STUB = 0
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default TTYS0_BAUD = 115200
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default TTYS0_BASE = 0x3f8
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default TTYS0_LCS = 0x3 # 8n1
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default DEFAULT_CONSOLE_LOGLEVEL = 9
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default MAXIMUM_CONSOLE_LOGLEVEL = 9
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default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
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end
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@ -0,0 +1,163 @@
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/*
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* This file is part of the coreboot project.
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*
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* Written by Stefan Reinauer <stepan@openbios.org>.
|
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* ACPI FADT, FACS, and DSDT table support added by
|
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*
|
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* Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
|
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* Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
|
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License v2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <../../../southbridge/via/vt8237r/vt8237r.h>
|
||||
#include <../../../southbridge/via/k8t890/k8t890.h>
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|
||||
extern unsigned char AmlCode[];
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||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
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{
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device_t dev;
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||||
struct resource *res;
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||||
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dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
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if (!dev)
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return current;
|
||||
|
||||
res = find_resource(dev, K8T890_MMCONFIG_MBAR);
|
||||
if (res) {
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
|
||||
current, res->base, 0x0, 0x0, 0xff);
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||||
}
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
unsigned int gsi_base = 0x18;
|
||||
|
||||
/* Create all subtables for processors. */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB IOAPIC. */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
VT8237R_APIC_ID, VT8237R_APIC_BASE, 0);
|
||||
|
||||
/* Write NB IOAPIC. */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
|
||||
|
||||
/* IRQ9 ACPI active low. */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
|
||||
|
||||
/* IRQ0 -> APIC IRQ2. */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0x0);
|
||||
|
||||
/* Create all subtables for processors. */
|
||||
current = acpi_create_madt_lapic_nmis(current,
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long write_acpi_tables(unsigned long start)
|
||||
{
|
||||
unsigned long current;
|
||||
acpi_rsdp_t *rsdp;
|
||||
acpi_srat_t *srat;
|
||||
acpi_rsdt_t *rsdt;
|
||||
acpi_mcfg_t *mcfg;
|
||||
acpi_hpet_t *hpet;
|
||||
acpi_madt_t *madt;
|
||||
acpi_fadt_t *fadt;
|
||||
acpi_facs_t *facs;
|
||||
acpi_header_t *dsdt;
|
||||
|
||||
/* Align ACPI tables to 16 byte. */
|
||||
start = (start + 0x0f) & -0x10;
|
||||
current = start;
|
||||
|
||||
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT table. */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
|
||||
/* Clear all table memory. */
|
||||
memset((void *) start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt);
|
||||
acpi_write_rsdt(rsdt);
|
||||
|
||||
/* We explicitly add these tables later on: */
|
||||
printk_debug("ACPI: * FACS\n");
|
||||
facs = (acpi_facs_t *) current;
|
||||
current += sizeof(acpi_facs_t);
|
||||
acpi_create_facs(facs);
|
||||
|
||||
dsdt = (acpi_header_t *) current;
|
||||
current += ((acpi_header_t *) AmlCode)->length;
|
||||
memcpy((void *) dsdt, (void *) AmlCode,
|
||||
((acpi_header_t *) AmlCode)->length);
|
||||
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
|
||||
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
|
||||
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
|
||||
dsdt->length);
|
||||
printk_debug("ACPI: * FADT\n");
|
||||
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
|
||||
acpi_create_fadt(fadt, facs, dsdt);
|
||||
acpi_add_table(rsdt, fadt);
|
||||
|
||||
printk_debug("ACPI: * HPET\n");
|
||||
hpet = (acpi_hpet_t *) current;
|
||||
current += sizeof(acpi_hpet_t);
|
||||
acpi_create_hpet(hpet);
|
||||
acpi_add_table(rsdt, hpet);
|
||||
|
||||
/* If we want to use HPET timers Linux wants an MADT. */
|
||||
printk_debug("ACPI: * MADT\n");
|
||||
madt = (acpi_madt_t *) current;
|
||||
acpi_create_madt(madt);
|
||||
current += madt->header.length;
|
||||
acpi_add_table(rsdt, madt);
|
||||
|
||||
printk_debug("ACPI: * MCFG\n");
|
||||
mcfg = (acpi_mcfg_t *) current;
|
||||
acpi_create_mcfg(mcfg);
|
||||
current += mcfg->header.length;
|
||||
acpi_add_table(rsdt, mcfg);
|
||||
|
||||
printk_debug("ACPI: * SRAT\n");
|
||||
srat = (acpi_srat_t *) current;
|
||||
acpi_create_srat(srat);
|
||||
current += srat->header.length;
|
||||
acpi_add_table(rsdt, srat);
|
||||
|
||||
printk_info("ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2006 AMD
|
||||
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
* Copyright (C) 2006 MSI
|
||||
* (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
|
||||
* Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
|
||||
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
|
||||
|
||||
unsigned int get_sbdn(unsigned bus);
|
||||
|
||||
/* Used by raminit. */
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
/* Used by init_cpus and fidvid */
|
||||
#define K8_SET_FIDVID 1
|
||||
|
||||
/* If we want to wait for core1 done before DQS training, set it to 0. */
|
||||
#define K8_SET_FIDVID_CORE0_ONLY 1
|
||||
|
||||
#if K8_REV_F_SUPPORT == 1
|
||||
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
|
||||
#endif
|
||||
|
||||
/* #define DEBUG_SMBUS 1 */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
#include "superio/ite/it8712f/it8712f_early_serial.c"
|
||||
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
|
||||
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#define K8_4RANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/amdk8.h"
|
||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "southbridge/via/k8t890/k8t890_early_car.c"
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
|
||||
void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
print_info("NO HARD RESET. FIX ME!\n");
|
||||
}
|
||||
|
||||
void soft_reset(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
set_bios_reset();
|
||||
print_debug("soft reset \r\n");
|
||||
|
||||
/* PCI reset */
|
||||
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
|
||||
tmp |= 0x01;
|
||||
/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
|
||||
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
|
||||
|
||||
while (1) {
|
||||
/* daisy daisy ... */
|
||||
hlt();
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int get_sbdn(unsigned bus)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
|
||||
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
|
||||
return (dev >> 15) & 0x1f;
|
||||
}
|
||||
|
||||
void sio_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
/* unsigned last_boot_normal_x = last_boot_normal(); */
|
||||
/* FIXME */
|
||||
unsigned last_boot_normal_x = 1;
|
||||
|
||||
sio_init();
|
||||
it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
|
||||
print_info("now booting... fallback\r\n");
|
||||
|
||||
/* Is this a CPU only reset? Or is this a secondary CPU? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x)
|
||||
goto normal_image;
|
||||
else
|
||||
goto fallback_image;
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0. */
|
||||
/* Allow the HT devices to be found. */
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Is this a deliberate reset by the BIOS? */
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary CPU, how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
|
||||
normal_image:
|
||||
/* print_info("JMP normal image\r\n"); */
|
||||
|
||||
__asm__ __volatile__("jmp __normal_image":
|
||||
:"a" (bist), "b" (cpu_init_detectedx));
|
||||
|
||||
fallback_image:
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
}
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
msr_t msr;
|
||||
static const uint16_t spd_addr[] = {
|
||||
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
||||
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
||||
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset = 0;
|
||||
struct sys_info *sysinfo =
|
||||
(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
char *p;
|
||||
|
||||
sio_init();
|
||||
it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
|
||||
print_info("now booting... real_main\r\n");
|
||||
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
/* Halt if there was a built in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
setup_default_resource_map();
|
||||
setup_coherent_ht_domain();
|
||||
wait_all_core0_started();
|
||||
|
||||
print_info("now booting... Core0 started\r\n");
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* It is said that we should start core1 after all core0 launched. */
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
init_timer();
|
||||
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
print_debug_hex8(needs_reset);
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
print_debug_hex8(needs_reset);
|
||||
needs_reset |= k8t890_early_setup_ht();
|
||||
print_debug_hex8(needs_reset);
|
||||
|
||||
vt8237_early_network_init(NULL);
|
||||
vt8237_early_spi_init();
|
||||
|
||||
if (needs_reset) {
|
||||
print_debug_hex8(needs_reset);
|
||||
|
||||
print_debug("Xht reset -\r\n");
|
||||
soft_reset();
|
||||
print_debug("NO reset\r\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
|
||||
/* allow LDT STOP asserts */
|
||||
vt8237_sb_enable_fid_vid();
|
||||
|
||||
enable_fid_change();
|
||||
print_debug("after enable_fid_change\r\n");
|
||||
|
||||
/* FIXME does not work yet */
|
||||
// init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* Stop the APs so we can start them later in init. */
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl now. */
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
enable_smbus();
|
||||
memreset_setup();
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License v2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_asus_m2v_mx_se_ops;
|
||||
|
||||
struct mainboard_asus_m2v_mx_se_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 dual_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 reserved_memory
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 DDR400
|
||||
8 1 DDR333
|
||||
8 2 DDR266
|
||||
8 3 DDR200
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
|
||||
* (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* ISA portions taken from QEMU acpi-dsdt.dsl.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License v2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
|
||||
{
|
||||
/* Define the main processor.*/
|
||||
Scope (\_PR)
|
||||
{
|
||||
Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
|
||||
Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
|
||||
}
|
||||
|
||||
/* For now only define 2 power states:
|
||||
* - S0 which is fully on
|
||||
* - S5 which is soft off
|
||||
* Any others would involve declaring the wake up methods.
|
||||
*/
|
||||
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
|
||||
|
||||
/* Root of the bus hierarchy */
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* Top PCI device */
|
||||
Device (PCI0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x00)
|
||||
|
||||
/* PCI Routing Table */
|
||||
/* aaa */
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x000F0000, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
|
||||
Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
|
||||
Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
|
||||
Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
|
||||
Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
|
||||
Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
|
||||
Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */
|
||||
Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */
|
||||
Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
|
||||
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
|
||||
})
|
||||
|
||||
Device (PEGG)
|
||||
{
|
||||
Name (_ADR, 0x00020000)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x02)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
|
||||
})
|
||||
}
|
||||
|
||||
Device (PEX0)
|
||||
{
|
||||
Name (_ADR, 0x00030000)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x03)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
|
||||
})
|
||||
}
|
||||
|
||||
Device (PEX1)
|
||||
{
|
||||
Name (_ADR, 0x00130000)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x4)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 },
|
||||
})
|
||||
}
|
||||
|
||||
Device (TBRG)
|
||||
{
|
||||
Name (_ADR, 0x00130001)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x5)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */
|
||||
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */
|
||||
Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
|
||||
})
|
||||
}
|
||||
Device (ISA) {
|
||||
Name (_ADR, 0x00110000)
|
||||
|
||||
/* PS/2 keyboard (seems to be important for WinXP install) */
|
||||
Device (KBD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* PS/2 mouse */
|
||||
Device (MOU)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* PS/2 floppy controller */
|
||||
Device (FDC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0700"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () {
|
||||
IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
|
||||
IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
|
||||
IRQNoFlags () {6}
|
||||
DMA (Compatibility, NotBusMaster, Transfer8) {2}
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <../../../southbridge/via/vt8237r/vt8237r.h>
|
||||
|
||||
/**
|
||||
* Create the Fixed ACPI Description Tables (FADT) for this board.
|
||||
*/
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = 244;
|
||||
header->revision = 1;
|
||||
memcpy(header->oem_id, "COREBO", 6);
|
||||
memcpy(header->oem_table_id, "COREBOOT", 8);
|
||||
memcpy(header->asl_compiler_id, "IASL", 4);
|
||||
header->asl_compiler_revision = 0;
|
||||
|
||||
fadt->firmware_ctrl = facs;
|
||||
fadt->dsdt = dsdt;
|
||||
fadt->preferred_pm_profile = 0;
|
||||
fadt->sci_int = 9;
|
||||
fadt->smi_cmd = 0;
|
||||
fadt->acpi_enable = 0;
|
||||
fadt->acpi_disable = 0;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0x0;
|
||||
|
||||
fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = 0x0;
|
||||
fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8;
|
||||
fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20;
|
||||
fadt->gpe1_blk = 0x0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 0;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 4;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0;
|
||||
fadt->p_lvl2_lat = 90;
|
||||
fadt->p_lvl3_lat = 900;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 0;
|
||||
fadt->duty_width = 1; //??
|
||||
fadt->day_alrm = 0x7d;
|
||||
fadt->mon_alrm = 0x7e;
|
||||
fadt->century = 0x32;
|
||||
/* fixme 5 - 10 */
|
||||
fadt->iapc_boot_arch = 0x1;
|
||||
/* fixme */
|
||||
fadt->flags = 0x4a5;
|
||||
|
||||
fadt->reset_reg.space_id = 0;
|
||||
fadt->reset_reg.bit_width = 0;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0x0;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 0;
|
||||
fadt->x_firmware_ctl_l = facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = VT8237R_ACPI_IO_BASE;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = VT8237R_ACPI_IO_BASE + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 4;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = VT8237R_ACPI_IO_BASE + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 0;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = VT8237R_ACPI_IO_BASE + 0x20;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License v2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if CONFIG_CHIP_NAME == 1
|
||||
struct chip_operations mainboard_asus_m2v_se_ops = {
|
||||
CHIP_NAME("ASUS M2V-MX SE Mainboard")
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License v2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <../../../southbridge/via/vt8237r/vt8237r.h>
|
||||
#include <../../../southbridge/via/k8t890/k8t890.h>
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
/* place holder for a table, need to have it defined because
|
||||
of MP_ used by ACPI */
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License v2 as published by
|
||||
## the Free Software Foundation.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
target asus_m2v-mx_se
|
||||
mainboard asus/m2v-mx_se
|
||||
|
||||
romimage "normal"
|
||||
option ROM_SIZE = 512 * 1024
|
||||
option USE_FALLBACK_IMAGE = 0
|
||||
option ROM_IMAGE_SIZE = 128 * 1024
|
||||
option COREBOOT_EXTRA_VERSION=".0Normal"
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE = 1
|
||||
option ROM_IMAGE_SIZE = 128 * 1024
|
||||
option COREBOOT_EXTRA_VERSION=".0Fallback"
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
|
||||
Loading…
Reference in New Issue