soc/intel/apl: Rework on CPU privilege level implementation

This patch migrates common code API into SoC specific implementation
to drop CPU privilege level as the MSR is not consistent across
platforms.

For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151.

Also, include `soc/msr.h` in cpu.h to fix the compilation issue.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/chip.c

@@ -28,6 +28,7 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/iomap.h>
 #include <soc/itss.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/systemagent.h>
@@ -702,10 +703,19 @@ struct chip_operations soc_intel_apollolake_ops = {
 	.final = &soc_final
 };
 
+static void soc_enable_untrusted_mode(void *unused)
+{
+	/*
+	 * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
+	 * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
+	 */
+	msr_set(MSR_POWER_MISC, ENABLE_IA_UNTRUSTED);
+}
+
 static void drop_privilege_all(void)
 {
 	/* Drop privilege level on all the CPUs */
-	if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL) != CB_SUCCESS)
+	if (mp_run_on_all_cpus(&soc_enable_untrusted_mode, NULL) != CB_SUCCESS)
 		printk(BIOS_ERR, "failed to enable untrusted mode\n");
 }
 

src/soc/intel/apollolake/include/soc/cpu.h

@@ -5,6 +5,7 @@
 
 #include <cpu/x86/msr.h>
 #include <intelblocks/msr.h>
+#include <soc/msr.h>
 
 struct device;
 void apollolake_init_cpus(struct device *dev);

src/soc/intel/apollolake/include/soc/msr.h

@@ -5,4 +5,8 @@
 
 #include <intelblocks/msr.h>
 
+#define MSR_POWER_MISC		0x120
+#define  ENABLE_IA_UNTRUSTED	(1 << 6)
+#define  FLUSH_DL1_L2		(1 << 8)
+
 #endif

src/soc/intel/common/block/cpu/cpulib.c

@@ -259,19 +259,6 @@ void cpu_set_eist(bool eist_status)
 	wrmsr(IA32_MISC_ENABLE, msr);
 }
 
-/*
- * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
- * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
- */
-void cpu_enable_untrusted_mode(void *unused)
-{
-	msr_t msr;
-
-	msr = rdmsr(MSR_POWER_MISC);
-	msr.lo |= ENABLE_IA_UNTRUSTED;
-	wrmsr(MSR_POWER_MISC, msr);
-}
-
 /*
  * This function fills in the number of Cores(physical) and Threads(virtual)
  * of the CPU in the function arguments. It also returns if the number of cores

src/soc/intel/common/block/include/intelblocks/cpulib.h

@@ -111,12 +111,6 @@ void cpu_burst_mode(bool burst_mode_status);
  */
 void cpu_set_eist(bool eist_status);
 
-/*
- * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
- * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
- */
-void cpu_enable_untrusted_mode(void *unused);
-
 /*
  * This function fills in the number of Cores(physical) and Threads(virtual)
  * of the CPU in the function arguments. It also returns if the number of cores

src/soc/intel/common/block/include/intelblocks/msr.h

@@ -17,9 +17,6 @@
 #define MSR_BIOS_UPGD_TRIG	0x7a
 #define  SGX_ACTIVATE_BIT	(1)
 #define MSR_PMG_IO_CAPTURE_BASE	0xe4
-#define MSR_POWER_MISC		0x120
-#define  ENABLE_IA_UNTRUSTED	(1 << 6)
-#define  FLUSH_DL1_L2		(1 << 8)
 #define MSR_EMULATE_PM_TIMER	0x121
 #define  EMULATE_DELAY_OFFSET_VALUE	20
 #define  EMULATE_PM_TMR_EN	(1 << 16)