Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
efdesign98
Marc Jones
parent
ee39ea7e7e
commit
05a89ab922
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@ -22,4 +22,4 @@ source src/cpu/amd/model_lx/Kconfig
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source src/cpu/amd/sc520/Kconfig
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source src/cpu/amd/agesa_wrapper/Kconfig
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source src/cpu/amd/agesa/Kconfig
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@ -14,5 +14,5 @@ subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
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subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
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subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
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subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper
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subdirs-$(CONFIG_AMD_AGESA) += agesa
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subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
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@ -17,4 +17,4 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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source src/cpu/amd/agesa_wrapper/family14/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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@ -16,4 +16,4 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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subdirs-$(CONFIG_CPU_AMD_AGESA_WRAPPER_FAMILY14) += family14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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@ -17,58 +17,58 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config CPU_AMD_AGESA_WRAPPER_FAMILY14
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config CPU_AMD_AGESA_FAMILY14
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bool
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select PCI_IO_CFG_EXT
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config CPU_ADDR_BITS
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int
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default 36
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config CPU_SOCKET_TYPE
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hex
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default 0x10
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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# DDR2 and REG
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config DIMM_SUPPORT
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hex
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default 0x0104
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config EXT_RT_TBL_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config EXT_CONF_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config CBB
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hex
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default 0x0
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config CDB
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hex
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default 0x18
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config XIP_ROM_BASE
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hex
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default 0xfff80000
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config XIP_ROM_SIZE
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hex
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default 0x80000
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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config HAVE_INIT_TIMER
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bool
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default y
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depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
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depends on CPU_AMD_AGESA_FAMILY14
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@ -16,7 +16,7 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ramstage-y += chip_name.c
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driver-y += model_14_init.c
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@ -279,4 +279,4 @@ subdirs-y += ../../../x86/pae
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subdirs-y += ../../../x86/smm
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ramstage-y += apic_timer.c
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cpu_incs += $(src)/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc
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cpu_incs += $(src)/cpu/amd/agesa/family14/cache_as_ram.inc
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@ -17,8 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct northbridge_amd_agesa_wrapper_family14_config
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{
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};
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extern struct chip_operations cpu_amd_agesa_family14_ops;
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extern struct chip_operations northbridge_amd_agesa_wrapper_family14_ops;
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struct cpu_amd_agesa_family14_config {
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};
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@ -20,6 +20,6 @@
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations cpu_amd_agesa_wrapper_family14_ops = {
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struct chip_operations cpu_amd_agesa_family14_ops = {
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CHIP_NAME("AMD CPU Family 14h")
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};
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@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select QRANK_DIMM_SUPPORT
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_AMD_RS780
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select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_WINBOND_W83627HF #COM1, COM2
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#select SUPERIO_FINTEK_F81216AD #COM3, COM4
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select HAVE_BUS_CONFIG
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@ -34,7 +34,7 @@ chip northbridge/amd/amdfam10/root_complex
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register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
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register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL
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end
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chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.2 on end # USB
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@ -112,7 +112,7 @@ chip northbridge/amd/amdfam10/root_complex
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#register "gpp_configuration" = "3" #2:1:1:0
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register "gpp_configuration" = "4" #1:1:1:1
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx_wrapper/sb800
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end #southbridge/amd/cimx/sb800
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end # device pci 18.0
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device pci 18.1 on end
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@ -49,7 +49,7 @@
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#include "southbridge/amd/rs780/early_setup.c"
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#include <SbEarly.h>
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#include <SBPLATFORM.h> /* SB OEM constants */
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#include <southbridge/amd/cimx_wrapper/sb800/smbus.h>
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#include <southbridge/amd/cimx/sb800/smbus.h>
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#include "northbridge/amd/amdfam10/debug.c"
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static void activate_spd_rom(const struct mem_controller *ctrl)
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@ -24,10 +24,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select ARCH_X86
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select DIMM_DDR3
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select DIMM_UNREGISTERED
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select CPU_AMD_AGESA_WRAPPER_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_SMSC_KBC1100
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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@ -16,17 +16,17 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa_wrapper/family14/root_complex
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/agesa_wrapper/family14
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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subsystemid 0x1022 0x1510 inherit
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chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
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chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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# device pci 18.0 on # northbridge
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chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge
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device pci 1.1 on end # Internal Multimedia
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@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 6.0 on end # PCIE P2P bridge 0x9606
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device pci 7.0 off end # PCIE P2P bridge 0x9607
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device pci 8.0 off end # NB/SB Link P2P bridge
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end # agesa_wrapper northbridge
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end # agesa northbridge
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chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.1 on end # USB
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@ -73,7 +73,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 15.3 on end # PCIe PortD
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register "gpp_configuration" = "4" #1:1:1:1
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx_wrapper/sb800
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end #southbridge/amd/cimx/sb800
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# end # device pci 18.0
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# These seem unnecessary
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device pci 18.0 on end
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@ -85,7 +85,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
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end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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end #pci_domain
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end #northbridge/amd/agesa_wrapper/family14/root_complex
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end #northbridge/amd/agesa/family14/root_complex
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@ -22,10 +22,10 @@ if BOARD_AMD_PERSIMMON
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_AGESA_WRAPPER_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_FINTEK_F81865F
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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@ -16,17 +16,17 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa_wrapper/family14/root_complex
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/agesa_wrapper/family14
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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subsystemid 0x1022 0x1510 inherit
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chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
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chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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# device pci 18.0 on # northbridge
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chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
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device pci 1.1 on end # Internal Multimedia
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@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 6.0 off end # PCIE P2P bridge 0x9606
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device pci 7.0 off end # PCIE P2P bridge 0x9607
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device pci 8.0 off end # NB/SB Link P2P bridge
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end # agesa_wrapper northbridge
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end # agesa northbridge
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chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.1 on end # USB
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@ -89,7 +89,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 15.3 off end # PCIe PortD
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register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx_wrapper/sb800
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end #southbridge/amd/cimx/sb800
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# end # device pci 18.0
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# These seem unnecessary
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device pci 18.0 on end
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@ -101,7 +101,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
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end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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end #pci_domain
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end #northbridge/amd/agesa_wrapper/family14/root_complex
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end #northbridge/amd/agesa/family14/root_complex
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@ -22,10 +22,10 @@ if BOARD_ASROCK_E350M1
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_AGESA_WRAPPER_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_WINBOND_W83627HF
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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@ -16,17 +16,17 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa_wrapper/family14/root_complex
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/agesa_wrapper/family14
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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subsystemid 0x1022 0x1510 inherit
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chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
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chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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# device pci 18.0 on # northbridge
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chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
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device pci 1.1 on end # Internal Multimedia
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@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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device pci 6.0 off end # PCIE P2P bridge 0x9606
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device pci 7.0 off end # PCIE P2P bridge 0x9607
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device pci 8.0 off end # NB/SB Link P2P bridge
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end # agesa_wrapper northbridge
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end # agesa northbridge
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chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.1 on end # USB
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@ -113,7 +113,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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register "gpp_configuration" = "4"
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx_wrapper/sb800
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end #southbridge/amd/cimx/sb800
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# end # device pci 18.0
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# These seem unnecessary
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device pci 18.0 on end
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|
|
@ -125,7 +125,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
|
|||
device pci 18.5 on end
|
||||
device pci 18.6 on end
|
||||
device pci 18.7 on end
|
||||
end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
|
||||
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
end #pci_domain
|
||||
end #northbridge/amd/agesa_wrapper/family14/root_complex
|
||||
end #northbridge/amd/agesa/family14/root_complex
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ source src/northbridge/amd/gx1/Kconfig
|
|||
source src/northbridge/amd/gx2/Kconfig
|
||||
source src/northbridge/amd/amdfam10/Kconfig
|
||||
source src/northbridge/amd/lx/Kconfig
|
||||
source src/northbridge/amd/agesa_wrapper/Kconfig
|
||||
source src/northbridge/amd/agesa/Kconfig
|
||||
menu "HyperTransport setup"
|
||||
#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
|
||||
depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
|
||||
|
|
|
|||
|
|
@ -4,5 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1
|
|||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
|
||||
|
||||
subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper
|
||||
subdirs-$(CONFIG_AMD_AGESA) += agesa
|
||||
subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
|
||||
|
|
|
|||
|
|
@ -17,4 +17,5 @@
|
|||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
source src/southbridge/amd/cimx_wrapper/sb800/Kconfig
|
||||
source src/northbridge/amd/agesa/family14/Kconfig
|
||||
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
|
||||
|
|
@ -16,12 +16,12 @@
|
|||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
|
||||
config NORTHBRIDGE_AMD_AGESA_FAMILY14
|
||||
bool
|
||||
select MMCONF_SUPPORT
|
||||
select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
|
||||
|
||||
if NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
|
||||
if NORTHBRIDGE_AMD_AGESA_FAMILY14
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
|
|
@ -41,6 +41,6 @@ config MMCONF_BUS_NUMBER
|
|||
|
||||
config BOOTBLOCK_NORTHBRIDGE_INIT
|
||||
string
|
||||
default "northbridge/amd/agesa_wrapper/family14/bootblock.c"
|
||||
default "northbridge/amd/agesa/family14/bootblock.c"
|
||||
|
||||
endif
|
||||
|
|
@ -17,7 +17,8 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations cpu_amd_agesa_wrapper_family14_ops;
|
||||
|
||||
struct cpu_amd_agesa_wrapper_family14_config {
|
||||
struct northbridge_amd_agesa_family14_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_family14_ops;
|
||||
|
|
@ -303,7 +303,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
|
|||
}
|
||||
|
||||
#if 0
|
||||
// We need to double check if there is speical set on base reg and limit reg
|
||||
// We need to double check if there is speical set on base reg and limit reg
|
||||
// are not continous instead of hole, it will find out it's hole_startk
|
||||
if(mem_hole.node_id==-1) {
|
||||
resource_t limitk_pri = 0;
|
||||
|
|
@ -324,7 +324,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
|
|||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
return mem_hole;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -459,7 +459,7 @@ static void set_resources(device_t dev)
|
|||
struct resource *res;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam14h - set_resources.\n");
|
||||
|
||||
|
||||
/* Find the nodeid */
|
||||
nodeid = amdfam14_nodeid(dev);
|
||||
|
||||
|
|
@ -749,11 +749,11 @@ static void domain_enable_resources(device_t dev)
|
|||
u32 val;
|
||||
/* Must be called after PCI enumeration and resource allocation */
|
||||
printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
|
||||
val = agesawrapper_amdinitmid ();
|
||||
val = agesawrapper_amdinitmid ();
|
||||
if(val) {
|
||||
printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
|
||||
}
|
||||
|
||||
|
||||
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
|
||||
}
|
||||
|
||||
|
|
@ -785,7 +785,7 @@ static void cpu_bus_set_resources(device_t dev)
|
|||
}
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
struct device_path cpu_path;
|
||||
|
|
@ -826,7 +826,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
|
|||
};
|
||||
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_wrapper_family14_ops = {
|
||||
struct chip_operations northbridge_amd_agesa_family14_ops = {
|
||||
CHIP_NAME("AMD Family 14h Northbridge")
|
||||
.enable_dev = 0,
|
||||
};
|
||||
|
|
@ -865,7 +865,7 @@ static void root_complex_enable_dev(struct device *dev)
|
|||
}
|
||||
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_wrapper_family14_root_complex_ops = {
|
||||
struct chip_operations northbridge_amd_agesa_family14_root_complex_ops = {
|
||||
CHIP_NAME("AMD Family 14h Root Complex")
|
||||
.enable_dev = root_complex_enable_dev,
|
||||
};
|
||||
|
|
@ -17,10 +17,10 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H
|
||||
#define NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H
|
||||
#ifndef NORTHBRIDGE_AMD_AGESA_FAM14H_H
|
||||
#define NORTHBRIDGE_AMD_AGESA_FAM14H_H
|
||||
|
||||
static struct device_operations pci_domain_ops;
|
||||
static struct device_operations cpu_bus_ops;
|
||||
|
||||
#endif /* NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H */
|
||||
#endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
config NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
|
||||
bool
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_agesa_family14_root_complex_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_family14_root_complex_ops;
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14) += family14
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
|
||||
bool
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_agesa_wrapper_family14_root_complex_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_wrapper_family14_root_complex_ops;
|
||||
|
|
@ -11,5 +11,5 @@ source src/southbridge/amd/sb600/Kconfig
|
|||
source src/southbridge/amd/rs780/Kconfig
|
||||
source src/southbridge/amd/sb700/Kconfig
|
||||
source src/southbridge/amd/sb800/Kconfig
|
||||
source src/southbridge/amd/cimx_wrapper/Kconfig
|
||||
source src/southbridge/amd/cimx/Kconfig
|
||||
source src/southbridge/amd/sr5650/Kconfig
|
||||
|
|
|
|||
|
|
@ -12,5 +12,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700
|
|||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
|
||||
subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx_wrapper
|
||||
subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx
|
||||
|
||||
|
|
|
|||
|
|
@ -17,5 +17,4 @@
|
|||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
source src/northbridge/amd/agesa_wrapper/family14/Kconfig
|
||||
|
||||
source src/southbridge/amd/cimx/sb800/Kconfig
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
|
||||
|
|
@ -17,13 +17,13 @@
|
|||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
|
||||
config SOUTHBRIDGE_AMD_CIMX_SB800
|
||||
bool
|
||||
select IOAPIC
|
||||
|
||||
if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
|
||||
if SOUTHBRIDGE_AMD_CIMX_SB800
|
||||
config BOOTBLOCK_SOUTHBRIDGE_INIT
|
||||
string
|
||||
default "southbridge/amd/cimx_wrapper/sb800/bootblock.c"
|
||||
endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
|
||||
default "southbridge/amd/cimx/sb800/bootblock.c"
|
||||
endif #SOUTHBRIDGE_AMD_CIMX_SB800
|
||||
|
||||
|
|
@ -17,10 +17,10 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CIMX_WRAPPER_SB800_CHIP_H_
|
||||
#define _CIMX_WRAPPER_SB800_CHIP_H_
|
||||
#ifndef _CIMX_SB800_CHIP_H_
|
||||
#define _CIMX_SB800_CHIP_H_
|
||||
|
||||
extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops;
|
||||
extern struct chip_operations southbridge_amd_cimx_sb800_ops;
|
||||
|
||||
/*
|
||||
* configuration set in mainboard/devicetree.cb
|
||||
|
|
@ -33,10 +33,10 @@ extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops;
|
|||
* 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
|
||||
* 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
|
||||
*/
|
||||
struct southbridge_amd_cimx_wrapper_sb800_config
|
||||
struct southbridge_amd_cimx_sb800_config
|
||||
{
|
||||
u32 boot_switch_sata_ide : 1;
|
||||
u8 gpp_configuration;
|
||||
};
|
||||
|
||||
#endif /* _CIMX_WRAPPER_SB800_CHIP_H_ */
|
||||
#endif /* _CIMX_SB800_CHIP_H_ */
|
||||
|
|
@ -20,6 +20,6 @@
|
|||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
|
||||
struct chip_operations southbridge_amd_cimx_sb800_ops = {
|
||||
CHIP_NAME("AMD South Bridge SB800")
|
||||
};
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
#include "lpc.h" /* lpc_read_resources */
|
||||
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
|
||||
#include "cfg.h" /* sb800 Cimx configuration */
|
||||
#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */
|
||||
#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
|
||||
|
||||
|
||||
/*implement in mainboard.c*/
|
||||
|
|
@ -316,8 +316,8 @@ static const struct pci_driver PORTD_driver __pci_driver = {
|
|||
*/
|
||||
static void sb800_enable(device_t dev)
|
||||
{
|
||||
struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
|
||||
(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
|
||||
struct southbridge_amd_cimx_sb800_config *sb_chip =
|
||||
(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
|
||||
|
||||
sb800_cimx_config(sb_config);
|
||||
printk(BIOS_DEBUG, "sb800_enable() ");
|
||||
|
|
@ -439,7 +439,7 @@ static void sb800_enable(device_t dev)
|
|||
|
||||
}
|
||||
|
||||
struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
|
||||
struct chip_operations southbridge_amd_cimx_sb800_ops = {
|
||||
CHIP_NAME("ATI SB800")
|
||||
.enable_dev = sb800_enable,
|
||||
};
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
|
|
@ -25,10 +25,10 @@
|
|||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
|
@ -145,7 +145,7 @@ WriteIo32 (
|
|||
{
|
||||
__outdword (Address, Data);
|
||||
}
|
||||
STATIC
|
||||
STATIC
|
||||
UINT64 SetFsBase (
|
||||
UINT64 address
|
||||
)
|
||||
|
|
@ -156,10 +156,10 @@ UINT64 SetFsBase (
|
|||
__writemsr (0xC0000100, address);
|
||||
return hwcr;
|
||||
}
|
||||
STATIC
|
||||
STATIC
|
||||
VOID
|
||||
RestoreHwcr (
|
||||
UINT64
|
||||
UINT64
|
||||
value
|
||||
)
|
||||
{
|
||||
|
|
@ -218,7 +218,7 @@ Write64Mem8 (
|
|||
{
|
||||
if ((Address >> 32) == 0){
|
||||
*(volatile UINT8 *) (UINTN) Address = Data;
|
||||
}
|
||||
}
|
||||
else {
|
||||
UINT64 hwcrSave;
|
||||
hwcrSave = SetFsBase (Address);
|
||||
|
|
@ -234,7 +234,7 @@ Write64Mem16 (
|
|||
{
|
||||
if ((Address >> 32) == 0){
|
||||
*(volatile UINT16 *) (UINTN) Address = Data;
|
||||
}
|
||||
}
|
||||
else {
|
||||
UINT64 hwcrSave;
|
||||
hwcrSave = SetFsBase (Address);
|
||||
|
|
@ -250,7 +250,7 @@ Write64Mem32 (
|
|||
{
|
||||
if ((Address >> 32) == 0){
|
||||
*(volatile UINT32 *) (UINTN) Address = Data;
|
||||
}
|
||||
}
|
||||
else {
|
||||
UINT64 hwcrSave;
|
||||
hwcrSave = SetFsBase (Address);
|
||||
|
|
@ -330,7 +330,7 @@ LibAmdHDTBreakPoint (
|
|||
)
|
||||
{
|
||||
__writemsr (0xC001100A, __readmsr (0xC001100A) | 1);
|
||||
__debugbreak (); // do you really need icebp? If so, go back to asm code
|
||||
__debugbreak (); // do you really need icebp? If so, go back to asm code
|
||||
}
|
||||
UINT8
|
||||
LibAmdBitScanForward (
|
||||
|
|
@ -387,7 +387,7 @@ ReadTSC (
|
|||
{
|
||||
return __rdtsc ();
|
||||
}
|
||||
VOID
|
||||
VOID
|
||||
LibAmdSimNowEnterDebugger (
|
||||
VOID
|
||||
)
|
||||
|
|
@ -416,7 +416,7 @@ VOID F10RevDProbeFilterCritical (
|
|||
_mm_mfence ();
|
||||
__outdword (0xCFC, PciRegister | 2);
|
||||
_mm_mfence ();
|
||||
__writemsr (0xC001001F, msrsave);
|
||||
__writemsr (0xC001001F, msrsave);
|
||||
}
|
||||
|
||||
VOID
|
||||
|
|
@ -447,7 +447,7 @@ IdsOutPort (
|
|||
{
|
||||
__outdword ((UINT16) Addr, Value);
|
||||
}
|
||||
VOID
|
||||
VOID
|
||||
StopHere (
|
||||
VOID
|
||||
)
|
||||
|
|
@ -765,7 +765,7 @@ LibAmdPciRead (
|
|||
LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
|
||||
} else {
|
||||
LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader);
|
||||
RMWrite = RMWritePrevious | 0x0000400000000000;
|
||||
RMWrite = RMWritePrevious | 0x0000400000000000ull;
|
||||
LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
|
||||
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
|
||||
LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
|
||||
|
|
@ -814,7 +814,7 @@ LibAmdPciWrite (
|
|||
LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
|
||||
} else {
|
||||
LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader);
|
||||
RMWrite = RMWritePrevious | 0x0000400000000000;
|
||||
RMWrite = RMWritePrevious | 0x0000400000000000ull;
|
||||
LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
|
||||
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
|
||||
LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
|
||||
|
|
@ -918,7 +918,7 @@ GetPciMmioAddress (
|
|||
MmioIsEnabled = FALSE;
|
||||
LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
|
||||
if ((MsrReg & BIT0) != 0) {
|
||||
*MmioAddress = MsrReg & 0xFFFFFFFFFFF00000;
|
||||
*MmioAddress = MsrReg & 0xFFFFFFFFFFF00000ull;
|
||||
EncodedSize = (UINT32) ((MsrReg & 0x3C) >> 2);
|
||||
*MmioSize = ((1 << EncodedSize) * 0x100000);
|
||||
MmioIsEnabled = TRUE;
|
||||
|
|
@ -1320,7 +1320,7 @@ LibAmdAccessWidth (
|
|||
return Width;
|
||||
}
|
||||
|
||||
VOID
|
||||
VOID
|
||||
CpuidRead (
|
||||
IN UINT32 CpuidFcnAddress,
|
||||
OUT CPUID_DATA *Value
|
||||
|
|
@ -1329,12 +1329,12 @@ CpuidRead (
|
|||
__cpuid ((int *)Value, CpuidFcnAddress);
|
||||
}
|
||||
|
||||
UINT8
|
||||
UINT8
|
||||
ReadNumberOfCpuCores(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
CPUID_DATA Value;
|
||||
CpuidRead (0x80000008, &Value);
|
||||
return Value.ECX_Reg & 0xff;
|
||||
return Value.ECX_Reg & 0xff;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
CIMX_ROOT = $(src)/vendorcode/amd/cimx
|
||||
|
||||
CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800
|
||||
CIMX_INC += -I$(src)/southbridge/amd/cimx/sb800
|
||||
CIMX_INC += -I$(CIMX_ROOT)/sb800
|
||||
|
||||
romstage-y += ACPILIB.c
|
||||
|
|
|
|||
Loading…
Reference in New Issue