sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers
If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL. The existing Lynx Point systems probably don't end up dereferencing NULL pointers this way. However, it might occur on a system using Flexible I/O to remap PCIe root ports to other functions. Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues presented themselves. Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30079 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -14,6 +14,8 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -22,6 +24,8 @@
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#include <device/pci_ops.h>
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#include "pch.h"
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#include <southbridge/intel/common/gpio.h>
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#include <stddef.h>
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#include <stdint.h>
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#define MAX_NUM_ROOT_PORTS 8
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@ -68,6 +72,16 @@ static inline int root_port_number(struct device *dev)
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return PCI_FUNC(dev->path.pci.devfn) + 1;
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}
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static bool is_rp_enabled(int rp)
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{
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ASSERT(rp > 0 && rp <= ARRAY_SIZE(rpc.ports));
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if (rpc.ports[rp - 1] == NULL)
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return false;
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return rpc.ports[rp - 1]->enabled;
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}
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static void root_port_config_update_gbe_port(void)
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{
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/* Is the Gbe Port enabled? */
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@ -163,7 +177,7 @@ static void pch_pcie_device_set_func(int index, int pci_func)
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/* Determine the new devfn for this port */
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new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, pci_func);
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if (dev->path.pci.devfn != new_devfn) {
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if (dev && dev->path.pci.devfn != new_devfn) {
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printk(BIOS_DEBUG,
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"PCH: PCIe map %02x.%1x -> %02x.%1x\n",
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PCI_SLOT(dev->path.pci.devfn),
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@ -188,9 +202,12 @@ static void pcie_enable_clock_gating(void)
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int rp;
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dev = rpc.ports[i];
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if (!dev)
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continue;
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rp = root_port_number(dev);
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if (!dev->enabled) {
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if (!is_rp_enabled(rp)) {
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static const uint32_t high_bit = (1UL << 31);
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/* Configure shared resource clock gating. */
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@ -198,17 +215,13 @@ static void pcie_enable_clock_gating(void)
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pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
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if (!is_lp) {
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if (rp == 1 && !rpc.ports[1]->enabled &&
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!rpc.ports[2]->enabled &&
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!rpc.ports[3]->enabled) {
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if (rp == 1 && !is_rp_enabled(2) &&
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!is_rp_enabled(3) && !is_rp_enabled(4)) {
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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}
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if (rp == 5 && !rpc.ports[5]->enabled &&
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(rpc.ports[6] == NULL ||
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!rpc.ports[6]->enabled) &&
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(rpc.ports[7] == NULL ||
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!rpc.ports[7]->enabled)) {
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if (rp == 5 && !is_rp_enabled(6) &&
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!is_rp_enabled(7) && !is_rp_enabled(8)) {
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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}
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@ -223,8 +236,8 @@ static void pcie_enable_clock_gating(void)
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pci_update_config32(dev, 0x420, ~0, (3 << 29));
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/* Enable static clock gating. */
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if (rp == 1 && !rpc.ports[1]->enabled &&
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!rpc.ports[2]->enabled && !rpc.ports[3]->enabled) {
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if (rp == 1 && !is_rp_enabled(2) &&
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!is_rp_enabled(3) && !is_rp_enabled(4)) {
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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} else if (rp == 5 || rp == 6) {
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@ -258,7 +271,7 @@ static void pcie_enable_clock_gating(void)
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pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
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}
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if (!enabled_ports && is_lp)
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if (!enabled_ports && is_lp && rpc.ports[0])
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pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
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}
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@ -267,7 +280,7 @@ static void root_port_commit_config(void)
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int i;
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/* If the first root port is disabled the coalesce ports. */
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if (!rpc.ports[0]->enabled)
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if (!is_rp_enabled(1))
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rpc.coalesce = 1;
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/* Perform clock gating configuration. */
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@ -307,7 +320,7 @@ static void root_port_commit_config(void)
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* function numbers. */
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current_func = 0;
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for (i = 0; i < rpc.num_ports; i++) {
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if (!rpc.ports[i]->enabled)
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if (!is_rp_enabled(i + 1))
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continue;
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pch_pcie_device_set_func(i, current_func);
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current_func++;
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@ -315,7 +328,7 @@ static void root_port_commit_config(void)
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/* Allocate the disabled devices' PCI function number. */
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for (i = 0; i < rpc.num_ports; i++) {
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if (rpc.ports[i]->enabled)
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if (is_rp_enabled(i + 1))
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continue;
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pch_pcie_device_set_func(i, current_func);
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current_func++;
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