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mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 ms 

Add 20ms adjust timing for edp panel in devicetree.

BUG=b:118011567
TEST=verify panel sequences by ODM.

Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29473
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2018-11-05 21:51:55 +08:00 committed by Martin Roth
parent 50c11607a1
commit 05b7cab1d7
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/kahlee/variants/liara/devicetree.cb
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@ -20,6 +20,8 @@ chip soc/amd/stoneyridge
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB"
register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms
register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{