boot to kernel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
37784b429d
commit
05c0869fac
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@ -169,7 +169,7 @@ cpuRegInit (void){
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/* */
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/* FooGlue Setup*/
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/* */
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#if 0
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#if 1
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/* Enable CIS mode B in FooGlue*/
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msrnum = MSR_FG + 0x10;
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msr = rdmsr(msrnum);
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@ -6,88 +6,29 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#if 0
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#include <cpu/amd/gx2def.h>
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#include <arch/io.h>
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static void gx2_cpu_setup(void)
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static void vsm_end_post_smi(void)
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{
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unsigned char rreg;
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unsigned char cpu_table[] = {
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0xc1, 0x00, /* NO SMIs */
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0xc3, 0x14, /* Enable CPU config register */
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0x20, 0x00, /* */
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0xb8, GX_BASE>>30, /* Enable GXBASE address */
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0xc2, 0x00,
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0xe8, 0x98,
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0xc3, 0xf8, /* Enable CPU config register */
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0x00, 0x00
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};
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unsigned char *cPtr = cpu_table;
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while(rreg = *cPtr++) {
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unsigned char rval = *cPtr++;
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outb(rreg, 0x22);
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outb(rval, 0x23);
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}
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outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
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if(inb(0x23) > 0x63) { /* Rev greater than R3 */
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outb(0xe8, 0x22);
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outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
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outb(0xf0, 0x22);
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outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
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outb(0x20, 0x22);
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outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
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/* Bit 2 Incrementor margin 10 */
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}
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__asm__ volatile (
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"push %ax\n"
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"mov $0x5000, %ax\n"
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".byte 0x0f, 0x38\n"
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"pop %ax\n"
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);
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}
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static void gx2_gx_setup(void)
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{
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unsigned long gx_setup_table[] = {
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GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
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GX_BASE + DC_GENERAL_CFG, 0,
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GX_BASE + DC_UNLOCK, 0,
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GX_BASE + BC_DRAM_TOP, 0x3fffffff,
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GX_BASE + BC_XMAP_1, 0x60,
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GX_BASE + BC_XMAP_2, 0,
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GX_BASE + BC_XMAP_3, 0,
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GX_BASE + MC_BANK_CFG, 0x00700070,
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GX_BASE + MC_MEM_CNTRL1, XBUSARB,
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GX_BASE + MC_GBASE_ADD, 0xff,
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0, 0
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};
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unsigned long *gxPtr = gx_setup_table;
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unsigned long *gxdPtr;
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unsigned long addr;
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while(addr = *gxPtr++) {
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gxdPtr = (unsigned long *)addr;
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*gxdPtr = *gxPtr++;
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}
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}
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#endif
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static void model_gx2_init(device_t dev)
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{
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void do_vsmbios(void);
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#if 0
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gx2_cpu_setup();
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gx2_gx_setup();
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#endif
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printk_debug("model_gx2_init\n");
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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/* Enable the local cpu apics */
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setup_lapic();
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//setup_lapic();
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vsm_end_post_smi();
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do_vsmbios();
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printk_debug("model_gx2_init DONE\n");
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};
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@ -96,7 +37,7 @@ static struct device_operations cpu_dev_ops = {
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_CYRIX, 0x0540 },
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{ X86_VENDOR_NSC, 0x0552 },
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{ 0, 0 },
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};
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@ -283,6 +283,10 @@ void do_vsmbios(void)
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/* ecx gets smm, edx gets sysm */
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printk_err("Call real_mode_switch_call_vsm\n");
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real_mode_switch_call_vsm(0x10000026, 0x10000028);
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/* restart timer 1 */
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outb(0x56, 0x43);
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outb(0x12, 0x41);
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}
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@ -448,6 +448,15 @@
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#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458
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#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459
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#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090
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#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091
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#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x2092
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#define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093
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#define PCI_DEVICE_ID_AMD_CS5536_OHCI 0x2094
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#define PCI_DEVICE_ID_AMD_CS5536_EHCI 0x2095
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#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096
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#define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097
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#define PCI_VENDOR_ID_TRIDENT 0x1023
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
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@ -124,20 +124,22 @@ dir /pc80
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config chip.h
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chip northbridge/amd/gx2
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/amd/cs5535
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device pci 12.0 on
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device pci 12.1 off end # SMI
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device pci 12.2 on end # IDE
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device pci 12.3 off end # Audio
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device pci 12.4 off end # VGA
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end
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end
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end
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chip cpu/amd/model_gx2
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end
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device apic_cluster 0 on
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chip cpu/amd/model_gx2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.4 on end # UHCI
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end
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end
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end
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@ -108,39 +108,14 @@ static void msr_init(void)
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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//__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
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//__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
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//__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
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//__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
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// __builtin_wrmsr(0x10000080, 0x3, 0x0);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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//__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
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//__builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
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//__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
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//__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
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//__builtin_wrmsr(0x50002001, 0x27, 0x0);
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//__builtin_wrmsr(0x4c002001, 0x1, 0x0);
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#if 1
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//__builtin_wrmsr(0x4c00000c, 0x0, 0x08);
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//__builtin_wrmsr(0x4c000016, 0x0, 0x0);
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//__builtin_wrmsr(0x4c00000c, 0x1, 0x0);
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//__builtin_wrmsr(0x4c00005e, 0x03880000, 0x00);
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//__builtin_wrmsr(0x4c00006f, 0x0000f000, 0x00);
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//__builtin_wrmsr(0x4c00005f, 0x08000000, 0x00);
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//__builtin_wrmsr(0x4c00000d, 0x82b5ad68, 0x80ad6b57);
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//__builtin_wrmsr(0x4c00000c, 0x0, 0x0);
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#endif
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}
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static void main(unsigned long bist)
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{
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msr_t msr;
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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uart_init();
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console_init();
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cs5535_early_setup();
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cs5536_early_setup();
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pll_reset();
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@ -161,10 +136,6 @@ static void main(unsigned long bist)
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sdram_initialize(1, memctrl);
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print_err("reading MSR 0x51102000\n\t");
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msr = rdmsr(0x51102000);
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print_debug_hex32(msr.hi);
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/* Check all of memory */
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//ram_check(0x00000000, 640*1024);
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}
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@ -124,20 +124,22 @@ dir /pc80
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config chip.h
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chip northbridge/amd/gx2
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/amd/cs5535
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device pci 12.0 on
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device pci 12.1 off end # SMI
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device pci 12.2 on end # IDE
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device pci 12.3 off end # Audio
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device pci 12.4 off end # VGA
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end
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end
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end
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chip cpu/amd/model_gx2
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end
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device apic_cluster 0 on
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chip cpu/amd/model_gx2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.4 on end # UHCI
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end
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end
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end
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@ -138,33 +138,9 @@ static void msr_init(void)
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
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__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
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__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x10000080, 0x3, 0x0);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
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__builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
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__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x50002001, 0x27, 0x0);
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__builtin_wrmsr(0x4c002001, 0x1, 0x0);
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#if 1
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__builtin_wrmsr(0x4c00000c, 0x0, 0x08);
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__builtin_wrmsr(0x4c000016, 0x0, 0x0);
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__builtin_wrmsr(0x4c00000c, 0x1, 0x0);
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__builtin_wrmsr(0x4c00005e, 0x03880000, 0x00);
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__builtin_wrmsr(0x4c00006f, 0x0000f000, 0x00);
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__builtin_wrmsr(0x4c00005f, 0x08000000, 0x00);
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__builtin_wrmsr(0x4c00000d, 0x82b5ad68, 0x80ad6b57);
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__builtin_wrmsr(0x4c00000c, 0x0, 0x0);
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#endif
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}
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@ -181,7 +157,7 @@ static void main(unsigned long bist)
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uart_init();
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console_init();
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cs5535_early_setup();
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cs5536_early_setup();
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pll_reset();
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@ -189,7 +165,6 @@ static void main(unsigned long bist)
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print_err("done cpuRegInit\n");
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sdram_initialize(1, memctrl);
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/* Check all of memory */
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//ram_check(0x00000000, 640*1024);
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@ -237,17 +237,6 @@ setup_gx2(void)
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}
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}
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static void optimize_xbus(device_t dev)
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{
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/* Optimise X-Bus performance */
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/* pci_write_config8(dev, 0x40, 0x1e);
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pci_write_config8(dev, 0x41, 0x52);
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pci_write_config8(dev, 0x43, 0xc1);
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pci_write_config8(dev, 0x44, 0x00);
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*/
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}
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static void enable_shadow(device_t dev)
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{
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@ -257,11 +246,9 @@ static void northbridge_init(device_t dev)
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{
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printk_debug("northbridge: %s()\n", __FUNCTION__);
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optimize_xbus(dev);
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enable_shadow(dev);
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}
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static struct device_operations northbridge_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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@ -273,12 +260,10 @@ static struct device_operations northbridge_operations = {
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &northbridge_operations,
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.vendor = PCI_VENDOR_ID_CYRIX,
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.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
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.vendor = PCI_VENDOR_ID_NS,
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.device = PCI_DEVICE_ID_NS_GX2,
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};
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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@ -441,7 +426,6 @@ static void enable_dev(struct device *dev)
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pci_set_method(dev);
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ram_resource(dev, 0, 0, (sizeram() - RAMADJUSTMB)*1024);
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} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
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dev->ops = &cpu_bus_ops;
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}
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