Silence unneeded #warnings, change to code comments (trіvial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -18,14 +18,19 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef IGNORE_I82801XX_DEVICE_LIST
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#warning "The i82801xx code currently supports, on a testing/experimental"
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#warning "basis, these devices:"
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#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm,"
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#warning "i82801eb, and i82801er."
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#warning "Using this without modification on any other i82801 version will"
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#warning "probably work until RAM init, but will fail after that."
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#endif
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/*
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* The i82801xx code currently supports:
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* - 82801AA
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* - 82801AB
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* - 82801BA
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* - 82801CA
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* - 82801DB
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* - 82801DBM
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* - 82801EB
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* - 82801ER
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*
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* This code should NOT be used for ICH6 and later versions.
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
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@ -43,10 +48,11 @@ struct southbridge_intel_i82801xx_config {
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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uint8_t ide0_enable;
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uint8_t ide1_enable;
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};
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extern struct chip_operations southbridge_intel_i82801xx_ops;
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#endif /* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */
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#endif
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