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soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake 

This patch ensures Skylake/Kabylake soc can make use of common
CSE code in order to perform global reset using HECI interface.

TEST=Build and boot on soraka/eve/reef/cnl-rvp

Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2017-11-09 15:04:09 +05:30 committed by Aaron Durbin
parent 330dc10cfd
commit 05e06cd0be
1 changed files with 22 additions and 3 deletions
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25
src/soc/intel/common/block/cse/cse.c
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@ -14,6 +14,7 @@
*/ */
#include <arch/early_variables.h> #include <arch/early_variables.h>
#include <assert.h>
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
@ -21,13 +22,11 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <string.h> #include <string.h>
#include <timer.h> #include <timer.h>
/* default window for early boot, must be at least 12 bytes in size */
#define HECI1_BASE_ADDRESS 0xfed1a000
/* Wait up to 15 sec for HECI to get ready */ /* Wait up to 15 sec for HECI to get ready */
#define HECI_DELAY_READY (15 * 1000) #define HECI_DELAY_READY (15 * 1000)
/* Wait up to 100 usec between circullar buffer polls */ /* Wait up to 100 usec between circullar buffer polls */
@ -108,15 +107,35 @@ void heci_init(uintptr_t tempbar)
cse->sec_bar = tempbar; cse->sec_bar = tempbar;
} }
/* Get HECI BAR 0 from PCI configuration space */
static uint32_t get_cse_bar(void)
{
uintptr_t bar;
bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0);
assert(bar != 0);
/*
* Bits 31-12 are the base address as per EDS for SPI,
* Don't care about 0-11 bit
*/
return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
}
static uint32_t read_bar(uint32_t offset) static uint32_t read_bar(uint32_t offset)
{ {
struct cse_device *cse = car_get_var_ptr(&g_cse); struct cse_device *cse = car_get_var_ptr(&g_cse);
/* Reach PCI config space to get BAR incase CAR global not available */
if (!cse->sec_bar)
cse->sec_bar = get_cse_bar();
return read32((void *)(cse->sec_bar + offset)); return read32((void *)(cse->sec_bar + offset));
} }
static void write_bar(uint32_t offset, uint32_t val) static void write_bar(uint32_t offset, uint32_t val)
{ {
struct cse_device *cse = car_get_var_ptr(&g_cse); struct cse_device *cse = car_get_var_ptr(&g_cse);
/* Reach PCI config space to get BAR incase CAR global not available */
if (!cse->sec_bar)
cse->sec_bar = get_cse_bar();
return write32((void *)(cse->sec_bar + offset), val); return write32((void *)(cse->sec_bar + offset), val);
} }