diff --git a/src/vendorcode/amd/fsp/mendocino/platform_descriptors.h b/src/vendorcode/amd/fsp/mendocino/platform_descriptors.h
index d86e5e1bc6..318a6abf9d 100644
--- a/src/vendorcode/amd/fsp/mendocino/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/mendocino/platform_descriptors.h
@@ -92,6 +92,7 @@ enum dxio_port_param_type {
 	PP_PHY_PARAM,
 	PP_ESM,
 	PP_CCIX,
+	PP_CXL,
 	PP_GEN3_DS_TX_PRESET,
 	PP_GEN3_DS_RX_PRESET_HINT,
 	PP_GEN3_US_TX_PRESET,
@@ -106,7 +107,37 @@ enum dxio_port_param_type {
 	PP_INVERT_POLARITY,
 	PP_TARGET_LINK_SPEED,
 	PP_GEN4_DLF_CAP_DISABLE,
-	PP_GEN4_DLF_EXCHG_DISABLE
+	PP_GEN4_DLF_EXCHG_DISABLE,
+	PP_I2C_EXPANDER_ADDRESS,
+	PP_I2C_EXPANDER_TYPE,
+	PP_UBM_SWITCH0_ADDR,
+	PP_UBM_SWITCH0_SELECT,
+	PP_UBM_SWITCH0_TYPE,
+	PP_UBM_SWITCH1_ADDR,
+	PP_UBM_SWITCH1_SELECT,
+	PP_UBM_SWITCH1_TYPE,
+	PP_UBM_HFC_INDEX,
+	PP_UBM_DFC_INDEX,
+	PP_GPIOx_I2C_RESET,
+	PP_GPIOx_BP_TYPE,
+	PP_START_LANE,
+	PP_OCP_PRESENT_START,
+	PP_OCP_PRESENT_COUNT,
+	PP_U3_PRESENT_PIN,
+	PP_U3_IFDET_PIN,
+	PP_U3_IFDET2_PIN,
+	PP_ALWAYS_EXPOSE,
+	PP_SRIS_ENABLED,
+	PP_SRIS_SKIP_INTERVAL,
+	PP_SRIS_LOWER_OS_GEN_SUP,
+	PP_SRIS_LOWER_OS_RCV_SUP,
+	PP_SRIS_AUTODETECT_MODE,
+	PP_SRIS_SKP_INTERVAL_SEL,
+	PP_SRIS_AUTODETECT_FACTOR,
+	PP_LEGACY_SWITCH0_ADDR,
+	PP_LEGACY_SWITCH0_SELECT,
+	PP_NPEM_ENABLE,
+	PP_NPEM_CAPABILITES,
 };
 
 /* DDI Aux channel */