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Replace cache control magic numbers with symbols 

Instead of opaque numbers like (1<<29), use
symbols like CR0_NoWriteThrough.

Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2012-03-31 12:52:21 +02:00 committed by Stefan Reinauer
parent 8919729307
commit 05e740fc40
11 changed files with 63 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/amd/agesa/cache_as_ram.inc
View File

@ -28,6 +28,7 @@
*/ */
#include "gcccar.inc" #include "gcccar.inc"
#include <cpu/x86/cache.h>
/* /*
* XMM map: * XMM map:
@ -88,7 +89,7 @@ disable_cache_as_ram:
/* Disable cache */ /* Disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
invd invd

3
src/cpu/amd/car/cache_as_ram.inc
View File

@ -19,6 +19,7 @@
*/ */
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheSize CONFIG_DCACHE_RAM_SIZE
@ -320,7 +321,7 @@ wbcache_post_fam10_setup:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
jmp_if_k8(fam10_end_part1) jmp_if_k8(fam10_end_part1)

4
src/cpu/amd/car/disable_cache_as_ram.c
View File

@ -21,12 +21,14 @@
* be warned, this file will be used other cores and core 0 / node 0 * be warned, this file will be used other cores and core 0 / node 0
*/ */
#include <cpu/x86/cache.h>
static inline __attribute__((always_inline)) void disable_cache_as_ram(void) static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{ {
msr_t msr; msr_t msr;
/* disable cache */ /* disable cache */
write_cr0(read_cr0() | (1 << 30)); write_cr0(read_cr0() | CR0_CacheDisable);
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;

7
src/cpu/intel/car/cache_as_ram.inc
View File

@ -23,6 +23,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic_def.h> #include <cpu/x86/lapic_def.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
@ -254,7 +255,7 @@ clear_fixed_var_mtrr_out:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl. */ /* Read the range with lodsl. */
@ -328,7 +329,7 @@ lout:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Clear sth. */ /* Clear sth. */
@ -353,7 +354,7 @@ lout:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Clear boot_complete flag. */ /* Clear boot_complete flag. */

17
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@ -22,6 +22,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cpu/x86/lapic_def.h> #include <cpu/x86/lapic_def.h>
@ -188,7 +189,7 @@ ap_init:
/* Do not disable cache (so BSP can enable it). */ /* Do not disable cache (so BSP can enable it). */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x28) post_code(0x28)
@ -271,7 +272,7 @@ no_msr_11e:
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd invd
movl %eax, %cr0 movl %eax, %cr0
@ -284,7 +285,7 @@ no_msr_11e:
/* Enable Cache-as-RAM mode by disabling cache. */ /* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x2d) post_code(0x2d)
@ -310,7 +311,7 @@ no_msr_11e:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x2e) post_code(0x2e)
@ -338,7 +339,7 @@ no_msr_11e:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x34) post_code(0x34)
@ -357,14 +358,14 @@ no_msr_11e:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x37) post_code(0x37)
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x38) post_code(0x38)
@ -393,7 +394,7 @@ no_msr_11e:
/* And enable cache again after setting MTRRs. */ /* And enable cache again after setting MTRRs. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x3a) post_code(0x3a)

15
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 32 #define CPU_MAXPHYADDR 32
@ -84,7 +85,7 @@ clear_mtrrs:
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd invd
movl %eax, %cr0 movl %eax, %cr0
@ -98,7 +99,7 @@ clear_mtrrs:
/* Enable Cache-as-RAM mode by disabling cache. */ /* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
#if CONFIG_XIP_ROM_SIZE #if CONFIG_XIP_ROM_SIZE
@ -122,7 +123,7 @@ clear_mtrrs:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Set up the stack pointer. */ /* Set up the stack pointer. */
@ -150,7 +151,7 @@ clear_mtrrs:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x31) post_code(0x31)
@ -181,14 +182,14 @@ clear_mtrrs:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x36) post_code(0x36)
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x38) post_code(0x38)
@ -207,7 +208,7 @@ clear_mtrrs:
/* And enable cache again after setting MTRRs. */ /* And enable cache again after setting MTRRs. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x3a) post_code(0x3a)

15
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <cbmem.h> #include <cbmem.h>
@ -98,7 +99,7 @@ clear_mtrrs:
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd invd
movl %eax, %cr0 movl %eax, %cr0
@ -126,7 +127,7 @@ clear_mtrrs:
post_code(0x26) post_code(0x26)
/* Enable Cache-as-RAM mode by disabling cache. */ /* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
@ -162,7 +163,7 @@ clear_mtrrs:
post_code(0x28) post_code(0x28)
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Set up the stack pointer below MRC variable space. */ /* Set up the stack pointer below MRC variable space. */
@ -195,7 +196,7 @@ before_romstage:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x31) post_code(0x31)
@ -235,14 +236,14 @@ before_romstage:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x36) post_code(0x36)
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x38) post_code(0x38)
@ -275,7 +276,7 @@ before_romstage:
/* And enable cache again after setting MTRRs. */ /* And enable cache again after setting MTRRs. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x3a) post_code(0x3a)

15
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 36 #define CPU_MAXPHYADDR 36
@ -84,7 +85,7 @@ clear_mtrrs:
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd invd
movl %eax, %cr0 movl %eax, %cr0
@ -98,7 +99,7 @@ clear_mtrrs:
/* Enable Cache-as-RAM mode by disabling cache. */ /* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
#if CONFIG_XIP_ROM_SIZE #if CONFIG_XIP_ROM_SIZE
@ -122,7 +123,7 @@ clear_mtrrs:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Set up the stack pointer. */ /* Set up the stack pointer. */
@ -150,7 +151,7 @@ clear_mtrrs:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x31) post_code(0x31)
@ -181,14 +182,14 @@ clear_mtrrs:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x36) post_code(0x36)
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x38) post_code(0x38)
@ -217,7 +218,7 @@ clear_mtrrs:
/* And enable cache again after setting MTRRs. */ /* And enable cache again after setting MTRRs. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x3a) post_code(0x3a)

15
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 36 #define CPU_MAXPHYADDR 36
@ -91,7 +92,7 @@ clear_mtrrs:
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd invd
movl %eax, %cr0 movl %eax, %cr0
@ -105,7 +106,7 @@ clear_mtrrs:
/* Enable Cache-as-RAM mode by disabling cache. */ /* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
#if CONFIG_XIP_ROM_SIZE #if CONFIG_XIP_ROM_SIZE
@ -129,7 +130,7 @@ clear_mtrrs:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Set up the stack pointer. */ /* Set up the stack pointer. */
@ -157,7 +158,7 @@ clear_mtrrs:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x31) post_code(0x31)
@ -188,14 +189,14 @@ clear_mtrrs:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x36) post_code(0x36)
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x38) post_code(0x38)
@ -214,7 +215,7 @@ clear_mtrrs:
/* And enable cache again after setting MTRRs. */ /* And enable cache again after setting MTRRs. */
movl %cr0, %eax movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0 movl %eax, %cr0
post_code(0x3a) post_code(0x3a)

9
src/cpu/via/car/cache_as_ram.inc
View File

@ -27,6 +27,7 @@
#include <cpu/x86/stack.h> #include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <console/post_codes.h> #include <console/post_codes.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheSize CONFIG_DCACHE_RAM_SIZE
@ -39,7 +40,7 @@ CacheAsRam:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
invd invd
@ -139,7 +140,7 @@ clear_fixed_var_mtrr_out:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl. */ /* Read the range with lodsl. */
@ -219,7 +220,7 @@ testok:
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Set the default memory type and enable variable MTRRs. */ /* Set the default memory type and enable variable MTRRs. */
@ -259,7 +260,7 @@ testok:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
invd invd

6
src/include/cpu/x86/cache.h
View File

@ -20,6 +20,11 @@
#ifndef CPU_X86_CACHE #ifndef CPU_X86_CACHE
#define CPU_X86_CACHE #define CPU_X86_CACHE
#define CR0_CacheDisable (1 << 30)
#define CR0_NoWriteThrough (1 << 29)
#if !defined(__ASSEMBLER__)
/* /*
* Need two versions because ROMCC chokes on certain clobbers: * Need two versions because ROMCC chokes on certain clobbers:
* cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
@ -107,4 +112,5 @@ static inline __attribute__((always_inline)) void disable_cache(void)
void x86_enable_cache(void); void x86_enable_cache(void);
#endif #endif
#endif /* !__ASSEMBLER__ */
#endif /* CPU_X86_CACHE */ #endif /* CPU_X86_CACHE */