diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 39572997c3..dc9caee9fb 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -211,6 +211,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
 	dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
 	m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
+
+	/* Change TmeEnable UPD value according to INTEL_TME Kconfig */
+	m_cfg->TmeEnable = CONFIG(INTEL_TME);
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)