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purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree 

Although VmxEnable is currently ignored by FSP, a forthcoming patch
explicitly enables it in coreboot, so set it in anticipation of that.

Enable Intel SpeedStep to ensure the ACPI tables are generated for
the C-states/P-states which are required for the xen-acpi-processor
module to be loaded. Without it, the Qubes 4.0-rc4 installer will
complain at boot about modules that could not be loaded.

Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Youness Alaoui 2018-02-09 18:44:45 -05:00 committed by Patrick Georgi
parent 59d89a8e59
commit 0601f1e164
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
View File

@ -7,6 +7,9 @@ chip soc/intel/skylake
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
register "eist_enable" = "1"
register "VmxEnable" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE

3
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
View File

@ -7,6 +7,9 @@ chip soc/intel/skylake
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
register "eist_enable" = "1"
register "VmxEnable" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE