device/pci: Enable full 16-bit VGA port i/o decoding
So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in silent conflicts we preallocated resources. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As older systems seem rather safe and well tested, and newer systems should support this bit, we'll use it if possible and only warn if not. With old (AGP era) hardware one will likely encounter a warning like this: found VGA at PCI: 06:00.0 A bridge on the path doesn't support 16-bit VGA decoding! This is not generally fatal, but makes unnoticed resource conflicts more likely. Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35516 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -759,6 +759,10 @@ static void set_vga_bridge_bits(void)
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continue;
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printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev));
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if (dev->bus->no_vga16) {
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printk(BIOS_WARNING,
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"A bridge on the path doesn't support 16-bit VGA decoding!");
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}
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if (dev->on_mainboard) {
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vga_onboard = dev;
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@ -797,7 +801,7 @@ static void set_vga_bridge_bits(void)
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while (bus) {
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printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
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dev_path(bus->dev));
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bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
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bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16;
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bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
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}
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}
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@ -792,6 +792,43 @@ struct device_operations default_pci_ops_bus = {
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.ops_pci = &pci_bus_ops_pci,
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};
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/**
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* Check for compatibility to route legacy VGA cycles through a bridge.
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*
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* Originally, when decoding i/o ports for legacy VGA cycles, bridges
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* should only consider the 10 least significant bits of the port address.
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* This means all VGA registers were aliased every 1024 ports!
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* e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
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*
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* To avoid this mess, a bridge control bit (VGA16) was introduced in
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* 2003 to enable decoding of 16-bit port addresses. As we don't want
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* to make this any more complex for now, we use this bit if possible
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* and only warn if it's not supported (in set_vga_bridge_bits()).
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*/
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static void pci_bridge_vga_compat(struct bus *const bus)
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{
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uint16_t bridge_ctrl;
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bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
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/* Ensure VGA decoding is disabled during probing (it should
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be by default, but we run blobs nowadays) */
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bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA;
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pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
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/* If the upstream bridge doesn't support VGA16, we don't have to check */
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bus->no_vga16 |= bus->dev->bus->no_vga16;
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if (bus->no_vga16)
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return;
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/* Test if we can enable 16-bit decoding */
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bridge_ctrl |= PCI_BRIDGE_CTL_VGA16;
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pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
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bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
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bus->no_vga16 = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16);
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}
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/**
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* Detect the type of downstream bridge.
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*
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@ -1293,6 +1330,8 @@ void do_pci_scan_bridge(struct device *dev,
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bus = dev->link_list;
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pci_bridge_vga_compat(bus);
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pci_bridge_route(bus, PCI_ROUTE_SCAN);
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do_scan_bus(bus, 0x00, 0xff);
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@ -94,6 +94,7 @@ struct bus {
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unsigned int reset_needed : 1;
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unsigned int disable_relaxed_ordering : 1;
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unsigned int ht_link_up : 1;
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unsigned int no_vga16 : 1; /* No support for 16-bit VGA decoding */
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};
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/*
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@ -138,6 +138,7 @@
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#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
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#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
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#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
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#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */
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#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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/* Fast Back2Back enabled on secondary interface */
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