GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Improving BKDG implementation of P-states, 

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran 2011-02-28 03:53:47 +00:00 committed by Marc Jones
parent c3132105bd
commit 061c89e15d
1 changed files with 0 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/cpu/amd/model_10xxx/fidvid.c
View File

@ -394,19 +394,6 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
} else { /* SVI */ } else { /* SVI */
/* set slamVidMode to 1 for SVI */ /* set slamVidMode to 1 for SVI */
dword |= VID_SLAM_ON; dword |= VID_SLAM_ON;
u32 dtemp = dword;
/* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
dword = pci_read_config32(dev, 0xD8);
if (dtemp & DUAL_VDD_BIT)
dword |= PWR_PLN_ON;
else
dword &= PWR_PLN_OFF;
pci_write_config32(dev, 0xD8, dword);
dword = dtemp;
} }
/* set the rest of A0 since we're at it... */ /* set the rest of A0 since we're at it... */