soc/intel/cannonlake: Add RP configuration settings
Add RP configuration settings like Advanced Error Reporting(AER), Latency Tolerence Reporting (LTR), Max Payload and Active State Power Management (ASPM). Tested on CFL platform Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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2 changed files with 36 additions and 1 deletions
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@ -181,6 +181,29 @@ struct soc_intel_cannonlake_config {
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/* Enable/Disable HotPlug support for Root Port */
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/* Enable/Disable HotPlug support for Root Port */
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uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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/*
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* Enable/Disable AER (Advanced Error Reporting) for Root Port
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* 0: Disable AER
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* 1: Enable AER
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*/
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uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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/* PCIE RP ASPM, ASPM support for the root port */
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enum {
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AspmDefault,
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AspmDisabled,
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AspmL0s,
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AspmL1,
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AspmL0sL1,
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AspmAutoConfig,
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} PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
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/* PCIE RP Max Payload, Max Payload Size supported */
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enum {
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RpMaxPayload_128,
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RpMaxPayload_256,
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} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
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/* eMMC and SD */
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/* eMMC and SD */
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uint8_t ScsEmmcHs400Enabled;
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uint8_t ScsEmmcHs400Enabled;
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/* Need to update DLL setting to get Emmc running at HS400 speed */
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/* Need to update DLL setting to get Emmc running at HS400 speed */
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@ -319,10 +319,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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sizeof(config->PcieClkSrcUsage));
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sizeof(config->PcieClkSrcUsage));
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memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
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memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
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sizeof(config->PcieClkSrcClkReq));
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sizeof(config->PcieClkSrcClkReq));
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memcpy(params->PcieRpAdvancedErrorReporting,
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config->PcieRpAdvancedErrorReporting,
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sizeof(params->PcieRpAdvancedErrorReporting));
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memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
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memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
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sizeof(config->PcieRpLtrEnable));
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sizeof(config->PcieRpLtrEnable));
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memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
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memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
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sizeof(config->PcieRpHotPlug));
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sizeof(params->PcieRpHotPlug));
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for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
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params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
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if (config->PcieRpAspm[i])
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params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
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};
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/* eMMC and SD */
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/* eMMC and SD */
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dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
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dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
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