mb/google/volteer: Modify Delbin variant
Update delbin configuration include GPIO, memory SPD table, I2C devices and USB type C. BUG=b:158797761 BRANCH=None TEST=emerge-volteer coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/42301 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen
Patrick Georgi
parent
2577407d03
commit
061f0d205b
|
|
@ -0,0 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
romstage-y += memory.c
|
||||
|
||||
bootblock-y += gpio.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config override_gpio_table[] = {
|
||||
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
|
||||
PAD_CFG_GPO(GPP_A7, 1, DEEP),
|
||||
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
|
||||
PAD_CFG_GPO(GPP_A10, 1, DEEP),
|
||||
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
|
||||
PAD_CFG_GPO(GPP_A13, 1, DEEP),
|
||||
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
/* A18 : DDSP_HPDB ==> HDMI_HPD */
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
|
||||
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
|
||||
/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
|
||||
PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
|
||||
/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
|
||||
PAD_CFG_GPO(GPP_A22, 1, DEEP),
|
||||
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
|
||||
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
|
||||
|
||||
/* B2 : VRALERT# ==> NC */
|
||||
PAD_NC(GPP_B2, NONE),
|
||||
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
/* B22 : GSPI1_MOSI ==> NC */
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
|
||||
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
|
||||
PAD_CFG_GPO(GPP_C0, 1, DEEP),
|
||||
/* C10 : UART0_RTS# ==> USI_RST_L */
|
||||
PAD_CFG_GPO(GPP_C10, 0, DEEP),
|
||||
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
|
||||
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
|
||||
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
|
||||
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
|
||||
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP),
|
||||
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
|
||||
PAD_CFG_GPO(GPP_D17, 1, DEEP),
|
||||
|
||||
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
|
||||
PAD_CFG_GPO(GPP_E3, 1, DEEP),
|
||||
/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
/* E7 : CPU_GP1 ==> USI_INT */
|
||||
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
|
||||
/* E8 : SPI1_CS1# ==> SLP_S0IX */
|
||||
PAD_CFG_GPO(GPP_E8, 0, DEEP),
|
||||
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
|
||||
/* E18 : DDP1_CTRLCLK ==> NC */
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
/* E20 : DDP2_CTRLCLK ==> NC */
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
|
||||
/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
|
||||
PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
|
||||
/* F11 : GPPF11_THC1_SPI2_CLK ==> NC */
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
|
||||
PAD_CFG_GPO(GPP_F13, 1, DEEP),
|
||||
|
||||
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_H3, 1, DEEP),
|
||||
/* H8 : I2C4_SDA ==> PCB_ID0 */
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
/* H9 : I2C4_SCL ==> PCB_ID1 */
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
/* H10 : SRCCLKREQ4# ==> NC */
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
/* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
|
||||
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
|
||||
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
|
||||
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX */
|
||||
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
|
||||
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
|
||||
/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
|
||||
/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
|
||||
/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
|
||||
|
||||
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
|
||||
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
|
||||
|
||||
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
|
||||
/* B11 : PMCALERT# ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
|
||||
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
|
||||
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
|
||||
PAD_CFG_GPO(GPP_C0, 1, DEEP),
|
||||
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_override_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(override_gpio_table);
|
||||
return override_gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
static const struct lpddr4x_cfg delbin_memcfg = {
|
||||
/* DQ byte map */
|
||||
.dq_map = {
|
||||
[0] = {
|
||||
{ 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */
|
||||
{ 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */
|
||||
},
|
||||
[1] = {
|
||||
{ 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */
|
||||
{ 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */
|
||||
},
|
||||
[2] = {
|
||||
{ 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */
|
||||
{ 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */
|
||||
},
|
||||
[3] = {
|
||||
{ 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */
|
||||
{ 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */
|
||||
},
|
||||
[4] = {
|
||||
{ 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */
|
||||
{ 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */
|
||||
},
|
||||
[5] = {
|
||||
{ 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */
|
||||
{ 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */
|
||||
},
|
||||
[6] = {
|
||||
{ 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */
|
||||
{ 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */
|
||||
},
|
||||
[7] = {
|
||||
{ 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */
|
||||
{ 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.dqs_map = {
|
||||
[0] = { 0, 1 }, /* DDR0_DQS[1:0] */
|
||||
[1] = { 0, 1 }, /* DDR1_DQS[1:0] */
|
||||
[2] = { 0, 1 }, /* DDR2_DQS[1:0] */
|
||||
[3] = { 0, 1 }, /* DDR3_DQS[1:0] */
|
||||
[4] = { 0, 1 }, /* DDR4_DQS[1:0] */
|
||||
[5] = { 0, 1 }, /* DDR5_DQS[1:0] */
|
||||
[6] = { 0, 1 }, /* DDR6_DQS[1:0] */
|
||||
[7] = { 0, 1 }, /* DDR7_DQS[1:0] */
|
||||
},
|
||||
|
||||
.ect = 1, /* Enable Early Command Training */
|
||||
};
|
||||
|
||||
const struct lpddr4x_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &delbin_memcfg;
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE
|
||||
SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A
|
||||
SPD_SOURCES += spd-2.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
DRAM Part Name ID to assign
|
||||
MT53E512M32D2NP-046 WT:E 0 (0000)
|
||||
MT53E1G32D2NP-046 WT:A 1 (0001)
|
||||
H9HCNNNBKMMLXR-NEE 0 (0000)
|
||||
H9HCNNNCPMMLXR-NEE 2 (0010)
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
MT53E512M32D2NP-046 WT:E
|
||||
MT53E1G32D2NP-046 WT:A
|
||||
H9HCNNNBKMMLXR-NEE
|
||||
H9HCNNNCPMMLXR-NEE
|
||||
|
|
@ -1,5 +1,82 @@
|
|||
chip soc/intel/tigerlake
|
||||
device domain 0 on
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
chip drivers/i2c/max98373
|
||||
register "vmon_slot_no" = "0"
|
||||
register "imon_slot_no" = "1"
|
||||
register "uid" = "0"
|
||||
register "desc" = ""Right Speaker Amp""
|
||||
register "name" = ""MAXR""
|
||||
device i2c 31 on end
|
||||
end
|
||||
chip drivers/i2c/max98373
|
||||
register "vmon_slot_no" = "2"
|
||||
register "imon_slot_no" = "3"
|
||||
register "uid" = "1"
|
||||
register "desc" = ""Left Speaker Amp""
|
||||
register "name" = ""MAXL""
|
||||
device i2c 32 on end
|
||||
end
|
||||
end
|
||||
device pci 15.1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN9008""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.disable_gpio_export_in_crs" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 10 on end
|
||||
end
|
||||
end # I2C1 0xA0E9
|
||||
device pci 19.1 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
register "probed" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end # I2C5 0xA0C6
|
||||
device pci 1f.2 hidden
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
register "usb2_port_number" = "9"
|
||||
register "usb3_port_number" = "1"
|
||||
# SBU is fixed, HSL follows CC
|
||||
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
register "usb2_port_number" = "4"
|
||||
register "usb3_port_number" = "2"
|
||||
# SBU is fixed, HSL follows CC
|
||||
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
device generic 1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # PMC
|
||||
end
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue