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nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUP 

Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten
some messages. This saves some KiB to make CBMEM console more
usable in romstage.

Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2017-04-15 15:57:28 +02:00 committed by Martin Roth
parent 35e6eb1cef
commit 0624f92118
4 changed files with 14 additions and 11 deletions
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1
src/northbridge/intel/gm45/gm45.h
View File

@ -443,6 +443,7 @@ struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);
#endif
#define RAM_DEBUG (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
#endif /* !__ACPI__ */
#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */

2
src/northbridge/intel/gm45/raminit.c
View File

@ -1593,7 +1593,7 @@ static void jedec_init(const timings_t *const timings,
/* We won't do this in dual-interleaved mode,
so don't care about the offset. */
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr);
printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2);
read32((u32 *)(rankaddr | WL));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3);

18
src/northbridge/intel/gm45/raminit_read_write_training.c
View File

@ -56,7 +56,7 @@ static void print_read_timing(const int msg_lvl, const char *const msg,
const int lane, const int channel,
const read_timing_t *const timing)
{
printk(msg_lvl, "%s for byte lane %d on channel %d: %d.%d\n",
printk(msg_lvl, "%sbyte lane %d, ch %d: %d.%d\n",
msg, lane, channel, timing->t, timing->p);
}
@ -187,7 +187,7 @@ static void read_training_per_lane(const int channel, const int lane,
lower.p = 0;
if (read_training_find_lower(channel, lane, addresses, &lower) < 0)
die("Read training failure: lower bound.\n");
print_read_timing(BIOS_SPEW, "Lower bound", lane, channel, &lower);
print_read_timing(RAM_DEBUG, "Lower bound for ", lane, channel, &lower);
/*** Search upper bound. ***/
@ -197,7 +197,7 @@ static void read_training_per_lane(const int channel, const int lane,
if (read_training_find_upper(channel, lane, addresses, &upper) < 0)
/* Overflow on upper edge is not fatal. */
printk(BIOS_WARNING, "Read training failure: upper bound.\n");
print_read_timing(BIOS_SPEW, "Upper bound", lane, channel, &upper);
print_read_timing(RAM_DEBUG, "Upper bound for ", lane, channel, &upper);
/*** Calculate and program mean value. ***/
@ -208,7 +208,8 @@ static void read_training_per_lane(const int channel, const int lane,
lower.t = mean_p >> READ_TIMING_P_SHIFT;
lower.p = mean_p & (READ_TIMING_P_BOUND - 1);
program_read_timing(channel, lane, &lower);
print_read_timing(BIOS_DEBUG, "Final timings", lane, channel, &lower);
printk(RAM_DEBUG, "Final timings for ");
print_read_timing(BIOS_DEBUG, "", lane, channel, &lower);
}
static void perform_read_training(const dimminfo_t *const dimms)
{
@ -351,7 +352,7 @@ static void print_write_timing(const int msg_lvl, const char *const msg,
const int group, const int channel,
const write_timing_t *const timing)
{
printk(msg_lvl, "%s for group %d on channel %d: %d.%d.%d\n",
printk(msg_lvl, "%sgroup %d, ch %d: %d.%d.%d\n",
msg, group, channel, timing->f, timing->t, timing->p);
}
@ -531,7 +532,7 @@ static void write_training_per_group(const int ch, const int group,
if (write_training_find_lower(ch, group, addresses,
masks, memclk1067, &lower) < 0)
die("Write training failure: lower bound.\n");
print_write_timing(BIOS_SPEW, "Lower bound", group, ch, &lower);
print_write_timing(RAM_DEBUG, "Lower bound for ", group, ch, &lower);
/*** Search upper bound. ***/
@ -543,7 +544,7 @@ static void write_training_per_group(const int ch, const int group,
if (write_training_find_upper(ch, group, addresses,
masks, memclk1067, &upper) < 0)
printk(BIOS_WARNING, "Write training failure: upper bound.\n");
print_write_timing(BIOS_SPEW, "Upper bound", group, ch, &upper);
print_write_timing(RAM_DEBUG, "Upper bound for ", group, ch, &upper);
/*** Calculate and program mean value. ***/
@ -557,7 +558,8 @@ static void write_training_per_group(const int ch, const int group,
lower.t = (mean_p >> WRITE_TIMING_P_SHIFT) % lower.t_bound;
lower.p = mean_p & (WRITE_TIMING_P_BOUND - 1);
program_write_timing(ch, group, &lower, memclk1067);
print_write_timing(BIOS_DEBUG, "Final timings", group, ch, &lower);
printk(RAM_DEBUG, "Final timings for ");
print_write_timing(BIOS_DEBUG, "", group, ch, &lower);
}
static void perform_write_training(const int memclk1067,
const dimminfo_t *const dimms)

4
src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
View File

@ -259,8 +259,8 @@ static void receive_enable_calibration(const timings_t *const timings,
rec_timings[ch][group].c - c_min;
rec_timings[ch][group].c = c_min;
program_timing(ch, group, rec_timings);
printk(BIOS_SPEW, "Final timings for group %d "
"on channel %d: %d.%d.%d.%d.%d\n",
printk(RAM_DEBUG, "Final timings for ");
printk(BIOS_DEBUG, "group %d, ch %d: %d.%d.%d.%d.%d\n",
group, ch,
rec_timings[ch][group].c,
rec_timings[ch][group].pre,