diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c
index 2440814f1d..6f7ae37743 100644
--- a/src/soc/mediatek/mt8183/dramc_init_setting.c
+++ b/src/soc/mediatek/mt8183/dramc_init_setting.c
@@ -1218,8 +1218,8 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
 		 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12)  |
 		 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
 	clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8);
-	clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0);
-	clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3200);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3200);
 
 	for (size_t rank = 0; rank < 2; rank++) {
 		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
@@ -1373,6 +1373,9 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
 	setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13));
 	clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0);
 
+	/* The default dramc init settings were tuned at frequency of 3200Mbps.
+	   For other frequencies uses dramc_setting_DDRxxx() to overwrite
+	   the default settings. */
 	switch (freq_group) {
 	case LP4X_DDR1600:
 		dramc_setting_DDR1600();
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 7242dd3ce8..aac6d17ed6 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -220,9 +220,7 @@ static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group,
 {
 	dramc_auto_refresh_switch(chn, false);
 
-	if (rank == RANK_0 && (freq_group == LP4X_DDR3600 ||
-			       freq_group == LP4X_DDR1600 ||
-			       freq_group == LP4X_DDR2400))
+	if (rank == RANK_0)
 		write_leveling_move_dqs_instead_of_clk(chn);
 
 	SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
@@ -265,8 +263,11 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group,
 	SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
 			SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly);
 
+	final_vref |= (1 << 6);
+
 	/* CBT set vref */
 	dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref);
+	dramc_dbg("final_vref: %#x\n", final_vref);
 }
 
 static void dramc_read_dbi_onoff(size_t chn, bool on)
@@ -1822,7 +1823,7 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group,
 			vref_end = vref_begin + 1;
 			dramc_dbg("bypass RX vref: %d\n", vref_begin);
 		} else if (type == TX_WIN_DQ_ONLY) {
-			vref_begin = params->tx_vref[chn][rank];
+			vref_begin = params->tx_vref[chn][rank] | (vref_range << 6);
 			vref_end = vref_begin + 1;
 			dramc_dbg("bypass TX vref: %d\n", vref_begin);
 		}
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
index 07b50d6585..66433602c5 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
@@ -74,12 +74,12 @@ enum {
 	DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1,
 	OEN_SHIFT = 16,
 
-	SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3),
-	SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1),
 	SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1),
 	SELPH_DQS1_1600 = _SELPH_DQS_BITS(0x1, 0x6),
 	SELPH_DQS0_2400 = _SELPH_DQS_BITS(0x3, 0x2),
 	SELPH_DQS1_2400 = _SELPH_DQS_BITS(0x1, 0x6),
+	SELPH_DQS0_3200 = _SELPH_DQS_BITS(0x3, 0x3),
+	SELPH_DQS1_3200 = _SELPH_DQS_BITS(0x5, 0x2),
 	SELPH_DQS0_3600 = _SELPH_DQS_BITS(0x4, 0x3),
 	SELPH_DQS1_3600 = _SELPH_DQS_BITS(0x1, 0x6),
 };