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mb/google/sarien/variants: Set tcc offset value 

Set tcc offset value to 5 degree celsius for Sarien system.

BRANCH=None
BUG=b:122636962
TEST=Built and tested on Sarien system

Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This commit is contained in:
Sumeet Pawnikar 2019-01-22 18:27:22 +05:30 committed by Patrick Georgi
parent d19f4e50aa
commit 062fdf13b8
2 changed files with 4 additions and 1 deletions
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3
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -70,6 +70,9 @@ chip soc/intel/cannonlake
#| I2C1 | Touchpad |
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
register "tcc_offset" = "5"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -75,7 +75,7 @@ chip soc/intel/cannonlake
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
register "tcc_offset" = "3"
register "tcc_offset" = "5"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,