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soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K 

The per-file hash for CBFS_VERIFICATION, stored as a CBFS file
attribute, would increase the total RO metadata size by 75% (3796->6656
for corsola). Therefore, in order to make RO metadata cache fit into
CBFS_MCACHE, enlarge it from 8K to 16K.

Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K
(only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also
shuffle the regions in SRAM with better comments.

BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel
BRANCH=none

Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Yu-Ping Wu 2022-04-28 17:35:40 +08:00 committed by Felix Held
parent f1a8dde147
commit 063355baef
1 changed files with 22 additions and 16 deletions
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38
src/soc/mediatek/mt8186/include/soc/memlayout.ld
View File

@ -21,33 +21,39 @@
SECTIONS SECTIONS
{ {
/* MT8186 has 64KB SRAM in total. */
SRAM_START(0x00100000) SRAM_START(0x00100000)
VBOOT2_WORK(0x00100000, 12K) /* Regions that need to stay in SRAM. */
TTB(0x00103000, 28K) TTB(0x00100000, 28K)
DMA_COHERENT(0x0010A000, 4K) DMA_COHERENT(0x00107000, 4K)
TPM_TCPA_LOG(0x0010B000, 2K) STACK(0x00108000, 10K)
FMAP_CACHE(0x0010B800, 2K) WATCHDOG_TOMBSTONE(0x0010a800, 4)
WATCHDOG_TOMBSTONE(0x0010C000, 4) /* EMPTY(0x0010a804, 1K - 4) */
CBFS_MCACHE(0x0010C004, 8K - 4) /* Regions that can also be moved to SRAM_L2C. */
STACK(0x0010E000, 7K) TIMESTAMP(0x0010ac00, 1K)
TIMESTAMP(0x0010FC00, 1K) TPM_TCPA_LOG(0x0010b000, 2K)
/* MT8186 has 64KB SRAM. */ FMAP_CACHE(0x0010b800, 2K)
CBFS_MCACHE(0x0010c000, 16K)
SRAM_END(0x00110000) SRAM_END(0x00110000)
/* /*
* The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM * The L3 (can be used as SRAM_L2C) is 1MB in total. However the bootROM has configured
* has configured only half of L2/L3 cache as SRAM and the rest for cache * only half of L2/L3 cache as SRAM and the rest for cache so we can't use them unless
* so we can't use them unless if we disable L2C and reconfigure (be aware * if we disable L2C and reconfigure (be aware we can't configure whole L3 to SRAM
* we can't configure whole L3 to SRAM without any cache). * without any cache).
*/ */
SRAM_L2C_START(0x00200000) SRAM_L2C_START(0x00200000)
/* 4K reserved for BOOTROM until BOOTBLOCK is started */ /*
* The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address
* is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started.
*/
BOOTBLOCK(0x00201000, 60K) BOOTBLOCK(0x00201000, 60K)
/* /*
* The needed size can be obtained by: * The needed size can be obtained by:
* aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
*/ */
DRAM_INIT_CODE(0x00210000, 196K) DRAM_INIT_CODE(0x00210000, 184K)
VBOOT2_WORK(0x0023e000, 12K)
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K)
PRERAM_CBFS_CACHE(0x00264000, 48K) PRERAM_CBFS_CACHE(0x00264000, 48K)
PRERAM_CBMEM_CONSOLE(0x00270000, 64K) PRERAM_CBMEM_CONSOLE(0x00270000, 64K)