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rambi: Update the DPTF configuration 

- Add passive thresholds for thermal participants
- Disable the charger participant and remove from _TRT

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi and start ESIF framework

Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181663
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5029
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Duncan Laurie 2014-01-06 12:35:36 -08:00 committed by Kyösti Mälkki
parent 766482d320
commit 063b2c4df7
1 changed files with 5 additions and 3 deletions
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8
src/mainboard/google/rambi/acpi/dptf.asl
View File

@ -1,11 +1,16 @@
#define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
#define DPTF_TSR0_PASSIVE 40
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 45
#define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR2_PASSIVE 35
#undef DPTF_ENABLE_CHARGER
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
@ -13,15 +18,12 @@ Name (DTRT, Package () {
/* CPU and Charger Effect on Temp Sensor 0 */ /* CPU and Charger Effect on Temp Sensor 0 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 80, 300, 0, 0, 0, 0 },
/* CPU and Charger Effect on Temp Sensor 1 */ /* CPU and Charger Effect on Temp Sensor 1 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 80, 300, 0, 0, 0, 0 },
/* CPU and Charger Effect on Temp Sensor 2 */ /* CPU and Charger Effect on Temp Sensor 2 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 80, 300, 0, 0, 0, 0 },
}) })
/* Include Baytrail DPTF */ /* Include Baytrail DPTF */