From 063c00c2e00b3457ac336763989a4b254345fb13 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 29 Jan 2018 11:45:21 -0700 Subject: [PATCH] soc/amd/stoneyridge: utilize full SPI flash controller fifo The spi flash host controller has a dedicated register for the opcode. Therefore, indicate to the spi subsystem that the opcode size should not be taken into account when determining maximum payload size in spi_crop_chunk(). This allows the full use of the fifo when doing transfers. BUG=b:65485690 Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/23492 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Justin TerAvest --- src/soc/amd/stoneyridge/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 9889727f06..b27d00ca74 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -193,7 +193,7 @@ static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, .xfer_vector = spi_xfer_two_vectors, .max_xfer_size = SPI_FIFO_DEPTH, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, + .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {