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soc/intel/skylake: Align PMC offset 0x31C name with CNL 

As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename
CIR31C with CPPMVRIC.

Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-28 17:55:02 +05:30
parent e37e668e5a
commit 063e933194
2 changed files with 3 additions and 3 deletions
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4
src/soc/intel/skylake/finalize.c
View File

@ -81,9 +81,9 @@ static void pch_finalize_script(struct device *dev)
/* Disable XTAL shutdown qualification for low power idle. */ /* Disable XTAL shutdown qualification for low power idle. */
if (config->s0ix_enable) { if (config->s0ix_enable) {
reg32 = read32(pmcbase + CIR31C); reg32 = read32(pmcbase + CPPMVRIC);
reg32 |= XTALSDQDIS; reg32 |= XTALSDQDIS;
write32(pmcbase + CIR31C, reg32); write32(pmcbase + CPPMVRIC, reg32);
} }
/* we should disable Heci1 based on the devicetree policy */ /* we should disable Heci1 based on the devicetree policy */

2
src/soc/intel/skylake/include/soc/pmc.h
View File

@ -82,6 +82,6 @@
#define GPE0_DW_SHIFT(x) (4*(x)) #define GPE0_DW_SHIFT(x) (4*(x))
#define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE0 0x124
#define GBLRST_CAUSE1 0x128 #define GBLRST_CAUSE1 0x128
#define CIR31C 0x31c #define CPPMVRIC 0x31c
#define XTALSDQDIS (1 << 22) #define XTALSDQDIS (1 << 22)
#endif #endif