soc/amd: Move global_smi_enable to common/blocks/smi/smi_util

Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/smi/smi_util.c

@@ -56,6 +56,15 @@ void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
 	smi_write32(SMI_REG_SMITRIG0, reg32);
 }
 
+/** Set the EOS bit and enable SMI generation from southbridge */
+void global_smi_enable(void)
+{
+	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
+	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
+	reg |= SMITRG0_EOS;	/* Set EOS bit */
+	smi_write32(SMI_REG_SMITRIG0, reg);
+}
+
 void soc_route_sci(uint8_t event)
 {
 	smi_write8(SMI_SCI_MAP(event), event);

src/soc/amd/picasso/Makefile.inc

@@ -48,7 +48,6 @@ ramstage-y += reset.c
 ramstage-y += acp.c
 ramstage-y += sata.c
 ramstage-y += memmap.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-y += uart.c
 ramstage-y += finalize.c
 ramstage-y += soc_util.c

src/soc/amd/picasso/smi.c

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * Utilities for SMM setup
- */
-
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <amdblocks/acpimmio.h>
-#include <soc/southbridge.h>
-#include <soc/smi.h>
-
-/** Set the EOS bit and enable SMI generation from southbridge */
-void global_smi_enable(void)
-{
-	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
-	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
-	reg |= SMITRG0_EOS;	/* Set EOS bit */
-	smi_write32(SMI_REG_SMITRIG0, reg);
-}

src/soc/amd/stoneyridge/Makefile.inc

@@ -58,7 +58,6 @@ ramstage-y += southbridge.c
 ramstage-y += northbridge.c
 ramstage-y += sata.c
 ramstage-y += memmap.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-y += uart.c
 ramstage-y += usb.c
 ramstage-y += tsc_freq.c

src/soc/amd/stoneyridge/smi.c

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * Utilities for SMM setup
- */
-
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <amdblocks/acpimmio.h>
-#include <soc/southbridge.h>
-#include <soc/smi.h>
-
-/** Set the EOS bit and enable SMI generation from southbridge */
-void global_smi_enable(void)
-{
-	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
-	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
-	reg |= SMITRG0_EOS;	/* Set EOS bit */
-	smi_write32(SMI_REG_SMITRIG0, reg);
-}