mb/google/octopus/variants/fleex: support LTE power sequence

GPIOs related to power sequence are
  GPIO_67  - EN_PP3300
  GPIO_117 - FULL_CARD_POWER_ON_OFF
  GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
  - keep GPIO_67 and GPIO_117 high and
  - pull down GPIO_161 for 30ms then release it.

BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/octopus/variants/fleex/Makefile.inc

@@ -1,3 +1,5 @@
 bootblock-y += gpio.c
 
 ramstage-y += gpio.c
+
+ramstage-y += variant.c

src/mainboard/google/octopus/variants/fleex/gpio.c

@@ -10,8 +10,10 @@ static const struct pad_config default_override_table[] = {
 
 	PAD_NC(GPIO_52, UP_20K),
 	PAD_NC(GPIO_53, UP_20K),
-	PAD_NC(GPIO_67, UP_20K),
+	/* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
-	PAD_NC(GPIO_117, UP_20K),
+	PAD_CFG_GPO(GPIO_67, 1, PWROK),
+	/* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
+	PAD_CFG_GPO(GPIO_117, 1, PWROK),
 
 	PAD_NC(GPIO_143, UP_20K),
 	PAD_NC(GPIO_144, UP_20K),
@@ -21,7 +23,8 @@ static const struct pad_config default_override_table[] = {
 	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
 					DISPUPD),
 
-	PAD_NC(GPIO_161, UP_20K),
+	/* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
+	PAD_CFG_GPO(GPIO_161, 1, DEEP),
 
 	PAD_NC(GPIO_213, DN_20K),
 	PAD_NC(GPIO_214, DN_20K),
@@ -33,3 +36,21 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
 
 	return default_override_table;
 }
+
+static const struct pad_config lte_early_override_table[] = {
+	/* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
+	PAD_CFG_GPO(GPIO_67, 1, PWROK),
+
+	/* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
+	PAD_CFG_GPO(GPIO_117, 1, PWROK),
+
+	/* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
+	PAD_CFG_GPO(GPIO_161, 0, DEEP),
+};
+
+const struct pad_config *variant_early_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(lte_early_override_table);
+
+	return lte_early_override_table;
+}

src/mainboard/google/octopus/variants/fleex/variant.c

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/variants.h>
+#include <delay.h>
+#include <gpio.h>
+
+struct gpio_with_delay {
+	gpio_t gpio;
+	unsigned int delay_msecs;
+};
+
+static void power_off_lte_module(u8 slp_typ)
+{
+	const struct gpio_with_delay lte_power_off_gpios[] = {
+		{
+			GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
+			30,
+		},
+		{
+			GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
+			100
+		},
+		{
+			GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
+			0
+		}
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) {
+		gpio_output(lte_power_off_gpios[i].gpio, 0);
+		mdelay(lte_power_off_gpios[i].delay_msecs);
+	}
+}
+
+void variant_smi_sleep(u8 slp_typ)
+{
+	/* Currently use cases here all target to S5 therefore we do early return
+	 * here for saving one transaction to the EC for getting SKU ID. */
+	if (slp_typ != ACPI_S5)
+		return;
+
+	power_off_lte_module(slp_typ);
+}