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cpu/x86/tsc: Compile TSC timer for postcar as well 

Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Andrey Petrov 2016-04-08 14:31:54 -07:00 committed by Martin Roth
parent 54e055179d
commit 064a50160a
1 changed files with 1 additions and 0 deletions
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src/cpu/x86/tsc/Makefile.inc
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@ -2,6 +2,7 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
endif