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southbridge/bd82x6x: Reserve 16 MiB for flash and not 8. 

X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash
but address map limits this to 16MiB.

Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-02-05 15:03:50 +01:00
parent 76998336aa
commit 0650cd0bad
1 changed files with 5 additions and 2 deletions
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7
src/southbridge/intel/bd82x6x/lpc.c
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@ -597,8 +597,11 @@ static void pch_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->base = 0xff000000;
/* Some systems (e.g. X230) have 12 MiB flash.
SPI controller supports up to 2 x 16 MiB of flash but
address map limits this to 16MiB. */
res->size = 0x01000000; /* 16 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;