Add support for DMP Vortex86EX PCI northbridge.
Change-Id: I60675a357f9db430ebb59b17be6d8c92a9cadf43 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Andrew Wu
Ronald G. Minnich
parent
378d04640d
commit
0651072597
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@ -1,4 +1,5 @@
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source src/northbridge/amd/Kconfig
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source src/northbridge/dmp/Kconfig
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source src/northbridge/intel/Kconfig
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source src/northbridge/rdc/Kconfig
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source src/northbridge/via/Kconfig
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@ -1,4 +1,5 @@
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subdirs-y += amd
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subdirs-y += dmp
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subdirs-y += intel
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subdirs-y += rdc
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subdirs-y += via
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@ -0,0 +1,20 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 DMP Electronics Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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source src/northbridge/dmp/vortex86ex/Kconfig
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@ -0,0 +1,20 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 DMP Electronics Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
|
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## the Free Software Foundation; version 2 of the License.
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||||
##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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subdirs-$(CONFIG_NORTHBRIDGE_DMP_VORTEX86EX) += vortex86ex
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 DMP Electronics Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config NORTHBRIDGE_DMP_VORTEX86EX
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bool
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 DMP Electronics Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ramstage-y += northbridge.c
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ramstage-y += xgi_oprom.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 DMP Electronics Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _NORTHBRIDGE_DMP_VORTEX86EX
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#define _NORTHBRIDGE_DMP_VORTEX86EX
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struct northbridge_dmp_vortex86ex_config {
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};
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#endif /* _NORTHBRIDGE_DMP_VORTEX86EX */
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@ -0,0 +1,146 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 DMP Electronics Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cbmem.h>
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#include <pc80/mc146818rtc.h>
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#include "chip.h"
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#include "northbridge.h"
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#define SPI_BASE 0xfc00
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static void northbridge_init(device_t dev)
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{
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printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n");
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// enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable.
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pci_write_config32(dev, NB_REG_MAR, 0x3ff000f0);
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// enable C0000h - C3FFFh/C4000h - C7FFF can be in L1 cache selection.
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pci_write_config32(dev, NB_REG_HOST_CTL, (1 << 18) | (1 << 19));
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// Set SPI register base.
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pci_write_config16(dev, NB_REG_SPI_BASE, SPI_BASE | 1);
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}
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static struct device_operations northbridge_operations = {
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init
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};
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static const struct pci_driver northbridge_driver_6021 __pci_driver = {
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.ops = &northbridge_operations,
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.vendor = PCI_VENDOR_ID_RDC,
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.device = 0x6021, /* DX CPU N/B ID */
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};
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static const struct pci_driver northbridge_driver_6025 __pci_driver = {
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.ops = &northbridge_operations,
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.vendor = PCI_VENDOR_ID_RDC,
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.device = 0x6025, /* EX CPU N/B ID */
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};
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/* Set CMOS register 15h/16h/17h/18h for base/extended
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* memory size. */
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static void set_cmos_memory_size(unsigned long sizek)
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{
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unsigned long ext_mem_size;
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u8 ext_mem_size_hb, ext_mem_size_lb;
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/* calculate memory size between 1M - 65M. */
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ext_mem_size = sizek - 1024;
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if (ext_mem_size > 65535)
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ext_mem_size = 65535;
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ext_mem_size_hb = (u8) (ext_mem_size >> 8);
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ext_mem_size_lb = (u8) (ext_mem_size & 0xff);
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/* Base memory is always 640K. */
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cmos_write(0x80, 0x15);
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cmos_write(0x02, 0x16);
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/* Write extended memory size. */
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cmos_write(ext_mem_size_lb, 0x17);
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cmos_write(ext_mem_size_hb, 0x18);
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/* register 0x30(48) is RTC_BOOT_BYTE for coreboot,
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* don't touch it. */
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}
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static void pci_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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uint32_t pci_tolm;
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printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n");
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pci_tolm = find_pci_tolm(dev->link_list);
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mc_dev = dev->link_list->children;
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if (mc_dev) {
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unsigned long tomk, tolmk;
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int idx;
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int ss;
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/* Get DDRII size setting from northbridge register. */
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/* SS = 0 for 2MB, 1 for 4MB, 2 for 8MB, 3 for 16MB ... */
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ss = pci_read_config16(mc_dev, 0x6c);
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ss = ((ss >> 8) & 0xf);
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tomk = (2 * 1024) << ss;
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printk(BIOS_DEBUG, "I would set ram size to %ld Mbytes\n", (tomk >> 10));
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk)
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/* The PCI hole does does not overlap the memory.
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*/
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tolmk = tomk;
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high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
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high_tables_size = HIGH_MEMORY_SIZE;
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printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
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tomk * 1024, high_tables_base, high_tables_size);
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640); /* first 640k */
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ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
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set_cmos_memory_size(tolmk);
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}
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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};
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static void enable_dev(struct device *dev)
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{
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printk(BIOS_SPEW, "In vortex86ex enable_dev for device %s.\n", dev_path(dev));
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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}
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}
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struct chip_operations northbridge_dmp_vortex86ex_ops = {
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CHIP_NAME("DMP Vortex86EX Northbridge")
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.enable_dev = enable_dev,
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};
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@ -0,0 +1,69 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 DMP Electronics Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef NORTHBRIDGE_H
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#define NORTHBRIDGE_H
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#define NB PCI_DEV(0, 0, 0)
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#define NB_REG_SPI_BASE 0x40
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#define NB_REG_CLK_OUT_CTL 0x48
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#define NB_REG_PCI_CLK_CTL 0x4b
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#define NB_REG_STRAP 0x60
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#define NB_REG_STRAP2 0x64
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#define NB_REG_MBR 0x6c
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#define NB_REG_DDR3_CFG 0x74
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#define NB_REG_DDR3_MTR1 0x78
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#define NB_REG_DDR3_MTR2 0x7c
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#define NB_REG_SMM 0x83
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#define NB_REG_MAR 0x84
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#define NB_REG_CID 0x90
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#define NB_REG_S1R 0x94
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#define NB_REG_S2R 0x98
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#define NB_REG_S3R 0x9c
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#define NB_REG_HOST_CTL 0xa0
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#define NB_REG_CPU_MBCR 0xc4
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#define NB_REG_CDR 0xd0
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#define NB_REG_PACR 0xf0
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#define NB_REG_PMCR 0xf4
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#define NB_REG_PCI_TARGET 0xf8
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#define NB_REG_PCSCR 0xfc
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/* Additional "virtual" device, just extension of NB */
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#define NB1 PCI_DEV(0, 0, 1)
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#define NB1_REG_FJZ_PHY_CTL1 0x80
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#define NB1_REG_FJZ_PHY_CTL2 0x84
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#define NB1_REG_FJZ_PHY_CTL3 0x88
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#define NB1_REG_FJZ_DRAM_CTL1 0x90
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#define NB1_REG_FJZ_DRAM_CTL2 0x94
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#define NB1_REG_FJZ_DRAM_CTL3 0x98
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#define NB1_REG_FJZ_DRAM_CTL4 0x9c
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#define NB1_REG_PLL_TEST_CTL 0xa8
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#define NB1_REG_DDR3_PWR_SAV 0xbc
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#define NB1_REG_DDR3_CTL_OPT1 0xc0
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#define NB1_REG_DDR3_CTL_OPT3 0xc8
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#define NB1_REG_DDR3_CTL_OPT4 0xcc
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#define NB1_REG_DDR3_CTL_OPT5 0xce
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#define NB1_REG_PLL_TEST_MODE 0xd0
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#define NB1_REG_L2_CACHE_CTL 0xe8
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#define NB1_REG_SSCR 0xec
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#define NB1_REG_NB_CTL_OPT1 0xf4
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#define NB1_REG_UPDATE_PHY_IO 0xf8
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#define NB1_REG_RESET_DRAMC_PHY 0xfa
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#endif /* NORTHBRIDGE_H */
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@ -0,0 +1,325 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 DMP Electronics Inc.
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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static u16 get_mask(u16 bit_width, u16 bit_offset)
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{
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u16 mask = (((1 << bit_width) - 1) << bit_offset);
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return mask;
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}
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static u16 set_bitfield(u16 val, u16 bits, u16 bit_width, u16 bit_offset)
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{
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u16 mask = get_mask(bit_width, bit_offset);
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val = (val & ~mask) | (bits << bit_offset);
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return val;
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}
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static u16 get_bitfield(u16 val, u16 bit_width, u16 bit_offset)
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{
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u16 mask = get_mask(bit_width, bit_offset);
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return (val & mask) >> bit_offset;
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}
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static u8 check_address_bit(int addr_bit)
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{
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u16 dummy;
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*(volatile u16 *)(0) = 0;
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dummy = *(volatile u16 *)(0); // read push write
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*(volatile u16 *)(1 << addr_bit) = 0x5a5a;
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dummy = *(volatile u16 *)(1 << addr_bit); // read push write
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if ((*(volatile u16 *)(0)) != 0)
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return 0; // address bit wrapped.
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return 1; // address bit not wrapped.
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}
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static u8 check_dram_side(int addr_bit)
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{
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*(volatile u16 *)(1 << addr_bit) = 0x5a5a;
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*(volatile u16 *)(0) = 0;
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if ((*(volatile u16 *)(1 << addr_bit)) != 0x5a5a)
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return 0; // DRAM only one side.
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return 1; // two sides.
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}
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// DDRIII memory bank register control:
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// bit :
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// 2 - 0 : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit
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// : 0 0 1 = 11bit
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// 7 - 5 : DRAMC_ROWSIZE : DDRIII Row Address Type : 0 0 0 = 13bit
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// : 0 0 1 = 14bit
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// : 0 1 0 = 15bit
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// : 0 1 1 = 16bit
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// 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M
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// : 0 1 1 0 = 128M
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// : 0 1 1 1 = 256M
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// : 1 0 0 0 = 512M
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// : 1 0 0 1 = 1GB
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// : 1 0 1 0 = 2GB
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// 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable
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#define DDR3_COL_10BIT 0
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#define DDR3_COL_11BIT 1
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#define DDR3_ROW_13BIT 0
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#define DDR3_ROW_14BIT 1
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#define DDR3_ROW_15BIT 2
|
||||
#define DDR3_ROW_16BIT 3
|
||||
#define DDR3_SIZE_64M 5
|
||||
#define DDR3_SIZE_128M 6
|
||||
#define DDR3_SIZE_256M 7
|
||||
#define DDR3_SIZE_512M 8
|
||||
#define DDR3_SIZE_1GB 9
|
||||
#define DDR3_SIZE_2GB 10
|
||||
#define DDR3_C1M_ACTIVE 0
|
||||
#define DDR3_C1M_MASK 1
|
||||
|
||||
static u16 set_ddr3_mem_reg_col(u16 reg, u16 col)
|
||||
{
|
||||
return set_bitfield(reg, col, 3, 0);
|
||||
}
|
||||
|
||||
static u16 get_ddr3_mem_reg_col(u16 reg)
|
||||
{
|
||||
return get_bitfield(reg, 3, 0);
|
||||
}
|
||||
|
||||
static u16 set_ddr3_mem_reg_row(u16 reg, u16 row)
|
||||
{
|
||||
return set_bitfield(reg, row, 3, 5);
|
||||
}
|
||||
|
||||
static u16 get_ddr3_mem_reg_row(u16 reg)
|
||||
{
|
||||
return get_bitfield(reg, 3, 5);
|
||||
}
|
||||
|
||||
static u16 set_ddr3_mem_reg_size(u16 reg, u16 size)
|
||||
{
|
||||
return set_bitfield(reg, size, 4, 8);
|
||||
}
|
||||
|
||||
static u16 get_ddr3_mem_reg_size(u16 reg)
|
||||
{
|
||||
return get_bitfield(reg, 4, 8);
|
||||
}
|
||||
|
||||
static u16 set_ddr3_mem_reg_c1m(u16 reg, u16 c1m)
|
||||
{
|
||||
return set_bitfield(reg, c1m, 1, 13);
|
||||
}
|
||||
|
||||
static u16 get_ddr3_mem_reg_c1m(u16 reg)
|
||||
{
|
||||
return get_bitfield(reg, 1, 13);
|
||||
}
|
||||
|
||||
static u16 auto_set_ddr3_mem_reg_size(u16 reg)
|
||||
{
|
||||
u8 ss = 0;
|
||||
// If reg is the minimum DRAM size,
|
||||
// SS is also the minimum size 128M.
|
||||
// If size in reg is bigger, SS is also bigger.
|
||||
ss += get_ddr3_mem_reg_col(reg);
|
||||
ss += get_ddr3_mem_reg_row(reg);
|
||||
ss += (1 - get_ddr3_mem_reg_c1m(reg));
|
||||
ss += DDR3_SIZE_128M;
|
||||
return set_ddr3_mem_reg_size(reg, ss);
|
||||
}
|
||||
|
||||
static u16 get_ddr3_mem_reg(u16 col, u16 row, u16 c1m)
|
||||
{
|
||||
u16 reg;
|
||||
reg = 0;
|
||||
reg = set_ddr3_mem_reg_col(reg, col);
|
||||
reg = set_ddr3_mem_reg_row(reg, row);
|
||||
reg = set_ddr3_mem_reg_c1m(reg, c1m);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void ddr3_phy_reset(void)
|
||||
{
|
||||
// PCI N/B reg FAh bit 6 = RST_DRAM_PHY.
|
||||
pci_write_config8(NB1, NB1_REG_RESET_DRAMC_PHY, 0x40);
|
||||
while ((pci_read_config8(NB1, NB1_REG_RESET_DRAMC_PHY) & 0x40) == 0x40) {
|
||||
}
|
||||
// reload mode.
|
||||
u32 ddr3_cfg = pci_read_config32(NB, NB_REG_DDR3_CFG);
|
||||
pci_write_config32(NB, NB_REG_DDR3_CFG, ddr3_cfg);
|
||||
}
|
||||
|
||||
static u8 detect_ddr3_dram_cs(u16 reg, u8 base_addr_bit)
|
||||
{
|
||||
reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_ACTIVE);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_dram_side(base_addr_bit + 1)) {
|
||||
base_addr_bit += 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_MASK);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
// no need to check CS = 0.
|
||||
// Need to reset DDR3 PHY.
|
||||
ddr3_phy_reset();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 detect_ddr3_dram_row(u16 reg, u8 base_addr_bit)
|
||||
{
|
||||
reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_16BIT);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_address_bit(base_addr_bit + 16)) {
|
||||
base_addr_bit += 16;
|
||||
return detect_ddr3_dram_cs(reg, base_addr_bit);
|
||||
}
|
||||
|
||||
reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_15BIT);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_address_bit(base_addr_bit + 15)) {
|
||||
base_addr_bit += 15;
|
||||
return detect_ddr3_dram_cs(reg, base_addr_bit);
|
||||
}
|
||||
|
||||
reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_14BIT);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_address_bit(base_addr_bit + 14)) {
|
||||
base_addr_bit += 14;
|
||||
return detect_ddr3_dram_cs(reg, base_addr_bit);
|
||||
}
|
||||
|
||||
reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_13BIT);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_address_bit(base_addr_bit + 13)) {
|
||||
base_addr_bit += 13;
|
||||
return detect_ddr3_dram_cs(reg, base_addr_bit);
|
||||
}
|
||||
// row test error.
|
||||
return 1;
|
||||
}
|
||||
|
||||
static u8 detect_ddr3_dram_bank(u16 reg, u8 base_addr_bit)
|
||||
{
|
||||
/* DDR3 is always 3 bank bits */
|
||||
base_addr_bit += 3;
|
||||
return detect_ddr3_dram_row(reg, base_addr_bit);
|
||||
}
|
||||
|
||||
static u8 detect_ddr3_dram_col(u16 reg, u8 base_addr_bit)
|
||||
{
|
||||
reg = set_ddr3_mem_reg_col(reg, DDR3_COL_11BIT);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_address_bit(base_addr_bit + 11)) {
|
||||
base_addr_bit += 11;
|
||||
return detect_ddr3_dram_bank(reg, base_addr_bit);
|
||||
}
|
||||
|
||||
reg = set_ddr3_mem_reg_col(reg, DDR3_COL_10BIT);
|
||||
reg = auto_set_ddr3_mem_reg_size(reg);
|
||||
pci_write_config16(NB, NB_REG_MBR, reg);
|
||||
if (check_address_bit(base_addr_bit + 10)) {
|
||||
base_addr_bit += 10;
|
||||
return detect_ddr3_dram_bank(reg, base_addr_bit);
|
||||
}
|
||||
// col test error.
|
||||
return 1;
|
||||
}
|
||||
|
||||
static u8 detect_ddr3_dram_size(void)
|
||||
{
|
||||
u16 reg;
|
||||
u8 base_addr_bit = 0;
|
||||
reg = get_ddr3_mem_reg(DDR3_COL_10BIT, DDR3_ROW_13BIT, DDR3_C1M_MASK);
|
||||
return detect_ddr3_dram_col(reg, base_addr_bit);
|
||||
}
|
||||
|
||||
static void print_ddr3_memory_setup(void)
|
||||
{
|
||||
#if CONFIG_DEBUG_RAM_SETUP
|
||||
print_debug("DDR3 Timing Reg 0-3:\n");
|
||||
print_debug("NB 6e : ");
|
||||
print_debug_hex16(pci_read_config16(NB, 0x6e));
|
||||
print_debug("\nNB 74 : ");
|
||||
print_debug_hex32(pci_read_config32(NB, 0x74));
|
||||
print_debug("\nNB 78 : ");
|
||||
print_debug_hex32(pci_read_config32(NB, 0x78));
|
||||
print_debug("\nNB 7c : ");
|
||||
print_debug_hex32(pci_read_config32(NB, 0x7c));
|
||||
u16 mbr = pci_read_config16(NB, 0x6c);
|
||||
print_debug("\nNB 6c(MBR) : ");
|
||||
print_debug_hex16(mbr);
|
||||
const char *s;
|
||||
u8 col = get_ddr3_mem_reg_col(mbr);
|
||||
if (col == DDR3_COL_10BIT)
|
||||
s = " (COL=10";
|
||||
else
|
||||
s = " (COL=11";
|
||||
print_debug(s);
|
||||
u8 row = get_ddr3_mem_reg_row(mbr);
|
||||
switch (row) {
|
||||
case DDR3_ROW_13BIT:
|
||||
s = ", ROW = 13";
|
||||
break;
|
||||
case DDR3_ROW_14BIT:
|
||||
s = ", ROW = 14";
|
||||
break;
|
||||
case DDR3_ROW_15BIT:
|
||||
s = ", ROW = 15";
|
||||
break;
|
||||
default:
|
||||
s = ", ROW = 16";
|
||||
break;
|
||||
}
|
||||
print_debug(s);
|
||||
u8 size = get_ddr3_mem_reg_size(mbr);
|
||||
switch (size) {
|
||||
case DDR3_SIZE_64M:
|
||||
s = ", 64M";
|
||||
break;
|
||||
case DDR3_SIZE_128M:
|
||||
s = ", 128M";
|
||||
break;
|
||||
case DDR3_SIZE_256M:
|
||||
s = ", 256M";
|
||||
break;
|
||||
case DDR3_SIZE_512M:
|
||||
s = ", 512M";
|
||||
break;
|
||||
case DDR3_SIZE_1GB:
|
||||
s = ", 1GB";
|
||||
break;
|
||||
case DDR3_SIZE_2GB:
|
||||
s = ", 2GB";
|
||||
break;
|
||||
}
|
||||
print_debug(s);
|
||||
u8 mask = get_ddr3_mem_reg_c1m(mbr);
|
||||
if (mask == DDR3_C1M_ACTIVE)
|
||||
s = ", CS MASK Enable)\n";
|
||||
else
|
||||
s = ", CS Mask Disable)\n";
|
||||
print_debug(s);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 DMP Electronics Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/********************************************************************
|
||||
* Change the vendor / device IDs to match the XGI Z9S VBIOS header.
|
||||
********************************************************************/
|
||||
#include <device/pci.h>
|
||||
u32 map_oprom_vendev(u32 vendev)
|
||||
{
|
||||
u32 new_vendev = vendev;
|
||||
|
||||
switch (vendev) {
|
||||
case 0x18ca0020:
|
||||
new_vendev = 0x18ca0021;
|
||||
break;
|
||||
}
|
||||
|
||||
return new_vendev;
|
||||
}
|
||||
Loading…
Reference in New Issue