Revert "soc/apollolake: Add soc core init"
This reverts commit a52f883b10
(https://review.coreboot.org/16587).
The above commit caused another sever kernel boot regression upwards
of 2 minutes to get through kernel init on quad core systems.
BUG=chrome-os-partner:58994
Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17121
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This commit is contained in:
parent
79daac9890
commit
06590a2014
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@ -461,7 +461,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
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silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
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silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
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silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
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silconfig->SkipMpInit = 1;
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/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
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/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
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silconfig->MonitorMwaitEnable = 0;
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silconfig->MonitorMwaitEnable = 0;
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@ -25,32 +25,11 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <reg_script.h>
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#include <soc/cpu.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/smm.h>
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#include <soc/smm.h>
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static const struct reg_script core_msr_script[] = {
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/* Enable C-state and IO/MWAIT redirect */
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REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL,
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(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
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| IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)),
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/* Power Management I/O base address for I/O trapping to C-states */
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REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,
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(ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),
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/* Disable C1E */
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REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
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REG_SCRIPT_END
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};
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static void soc_core_init(device_t cpu)
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{
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/* Set core MSRs */
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reg_script_run(core_msr_script);
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}
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static struct device_operations cpu_dev_ops = {
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static struct device_operations cpu_dev_ops = {
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.init = soc_core_init,
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.init = DEVICE_NOOP,
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};
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};
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static struct cpu_device_id cpu_table[] = {
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static struct cpu_device_id cpu_table[] = {
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@ -54,19 +54,6 @@ void apollolake_init_cpus(struct device *dev);
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*/
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*/
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#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e
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#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e
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/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
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#define PKG_C_STATE_LIMIT_C2_MASK 0x2
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/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
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#define CORE_C_STATE_LIMIT_C10_MASK 0x70
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/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
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#define IO_MWAIT_REDIRECT_MASK 0x400
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/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
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#define CST_CFG_LOCK_MASK 0x8000
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#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_CAPTURE_BASE 0xe4
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#define MSR_POWER_CTL 0x1fc
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#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
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#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
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#define MSR_IA32_PQR_ASSOC 0xc8f
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#define MSR_IA32_PQR_ASSOC 0xc8f
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/* MSR bits 33:32 encode slot number 0-3 */
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/* MSR bits 33:32 encode slot number 0-3 */
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@ -29,11 +29,6 @@
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#define ACPI_PMIO_SIZE 0x100
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#define ACPI_PMIO_SIZE 0x100
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#define R_ACPI_PM1_TMR 0x8
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#define R_ACPI_PM1_TMR 0x8
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/* CST Range (R/W) IO port block size */
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#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5
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/* ACPI PMIO Offset to C-state register*/
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#define ACPI_PMIO_CST_REG (ACPI_PMIO_BASE + 0x14)
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/* Accesses to these BARs are hardcoded in FSP */
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/* Accesses to these BARs are hardcoded in FSP */
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#define PMC_BAR0 0xfe042000
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#define PMC_BAR0 0xfe042000
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#define PMC_BAR1 0xfe044000
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#define PMC_BAR1 0xfe044000
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