mb/up/squared: Fix eMMC speed for UP2 with EDK2

Since commit 402fe20e (mb/up/squared: Add mainboard) the UP2's eMMC
maximum host speed was reduced to DDR50, because HS200 showed I/O errors
in the host kernel. We found out that with EDK2 master the correct
Host Speed could not be set properly during EDK2 platform init.
Therefore eMMC would not show up for boot device selection.

This commit sets the eMMC MaxHostSpeed to the designed max value of the
used eMMC on the UP2 board and furthermore drops the override from the
ramstage.c. It's already set in the devicetree.cb.

Though CRC errors are still visible in EDK II debug logs, no other
negative effects have been observed.

Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Change-Id: I8d53204d8a776efd560fbdea918f83e180813179
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/up/squared/devicetree.cb

@@ -16,6 +16,10 @@ chip soc/intel/apollolake
 
 	register "enable_vtd" = "1"
 
+	# Override eMMC MaxHostSpeed
+	# 0:HS400 (Default) 1:HS200 2:DDR50
+	register "emmc_host_max_speed" = "1"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end

src/mainboard/up/squared/ramstage.c

@@ -30,7 +30,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
 	silconfig->IoApicBdfValid = 0x1;		// 0x0
 	silconfig->IoApicDeviceNumber = 0x1F;		// 0xf
 	silconfig->LPSS_S0ixEnable = 0x1;		// 0x0
-	silconfig->eMMCHostMaxSpeed = 0x2;		// 0x0
 	silconfig->Usb30Mode = 0x1;			// 0x0
 	silconfig->HdAudioDspUaaCompliance = 0x1;	// 0x0
 	silconfig->InitS3Cpu = 0x1;			// 0x0