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google/reef: Add GPE routing settings 

This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.

BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
       and see that the sci counter increases in /sys/firmware/acpi/interrupt
       and also 9 in /proc/interrupt

Change-Id: If258bece12768edb1e612c982514ce95c756c438
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15556
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-07-06 15:50:48 -07:00 committed by Aaron Durbin
parent 6e5c5a15bc
commit 066e0f3923
3 changed files with 15 additions and 4 deletions
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9
src/mainboard/google/reef/devicetree.cb
View File

@ -36,6 +36,15 @@ chip soc/intel/apollolake
# 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200
register "emmc_rx_cmd_data_cntl2" = "0x1001C" register "emmc_rx_cmd_data_cntl2" = "0x1001C"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_31_0"
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF device pci 00.1 on end # - DPTF

8
src/mainboard/google/reef/ec.h
View File

@ -18,9 +18,11 @@
#include <ec/google/chromeec/ec_commands.h> #include <ec/google/chromeec/ec_commands.h>
/* This is the GPE status bit. /*
TODO: Fix this to proper bit matching GPE routing table */ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
#define EC_SCI_GPI 15 * which is North community
*/
#define EC_SCI_GPI GPE0_DW1_11
#define MAINBOARD_EC_SCI_EVENTS \ #define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\

2
src/mainboard/google/reef/gpio.h
View File

@ -282,7 +282,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */ PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */
PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI */ PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */
PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */