variants/kahlee: Add thermal ASL
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS thermal values in the mainboard finalize. BUG=b:67999819 Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <variant/thermal.h>
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/* Thermal Zone */
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Scope (\_TZ)
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{
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ThermalZone (THRM)
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{
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/* Thermal constants for passive cooling */
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Name (_TC1, 0x02)
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Name (_TC2, 0x05)
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/* Thermal zone polling frequency: 10 seconds */
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Name (_TZP, 100)
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/* Thermal sampling period for passive cooling: 2 seconds */
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Name (_TSP, 20)
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/* Convert from Degrees C to 1/10 Kelvin for ACPI */
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Method (CTOK, 1) {
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/* 10th of Degrees C */
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Multiply (Arg0, 10, Local0)
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/* Convert to Kelvin */
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Add (Local0, 2732, Local0)
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Return (Local0)
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}
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/* Threshold for OS to shutdown */
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Method (_CRT, 0, Serialized)
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{
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Return (CTOK (\TCRT))
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}
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/* Threshold for passive cooling */
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Method (_PSV, 0, Serialized)
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{
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Return (CTOK (\TPSV))
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}
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/* Processors used for passive cooling */
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Method (_PSL, 0, Serialized)
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{
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Return (\PPKG ())
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}
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Method (_TMP, 0, Serialized)
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{
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/* Get temperature from EC in deci-kelvin */
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Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
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/* Critical temperature in deci-kelvin */
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Store (CTOK (\TCRT), Local1)
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If (LGreaterEqual (Local0, Local1)) {
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Store ("CRITICAL TEMPERATURE", Debug)
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Store (Local0, Debug)
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/* Wait 1 second for EC to re-poll */
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Sleep (1000)
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/* Re-read temperature from EC */
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Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
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Store ("RE-READ TEMPERATURE", Debug)
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Store (Local0, Debug)
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}
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Return (Local0)
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}
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/* No active fan control (_ACx) on Kahlee */
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}
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}
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@ -77,6 +77,9 @@ DefinitionBlock (
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} /* End \_SB scope */
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} /* End \_SB scope */
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/* Thermal handler */
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#include "acpi/thermal.asl"
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/* Chrome OS specific */
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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@ -18,9 +18,12 @@
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#include <arch/acpi.h>
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#include <arch/acpi.h>
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#include <agesawrapper.h>
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#include <agesawrapper.h>
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#include <amd_pci_util.h>
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#include <amd_pci_util.h>
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#include <cbmem.h>
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#include <ec.h>
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#include <ec.h>
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <soc/nvs.h>
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#include <soc/smi.h>
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#include <soc/smi.h>
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#include <variant/thermal.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/***********************************************************
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/***********************************************************
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@ -104,7 +107,22 @@ static void kahlee_enable(device_t dev)
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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}
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}
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static void mainboard_final(void *chip_info)
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{
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struct global_nvs_t *gnvs;
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (gnvs) {
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gnvs->tmps = CTL_TDP_SENSOR_ID;
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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}
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struct chip_operations mainboard_ops = {
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.init = mainboard_init,
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.enable_dev = kahlee_enable,
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.enable_dev = kahlee_enable,
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.final = mainboard_final,
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};
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};
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef THERMAL_H
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#define THERMAL_H
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/*
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* Stoney Ridge Thermal Requirements 12 (6W)
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* TDP (W) 6
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* T die,max (°C) 95
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* T ctl,max 85
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* T die,lmt (default) 90
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* T ctl,lmt (default) 80
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*/
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/* Control TDP Settings */
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#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */
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/* Temperature which OS will shutdown at */
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#define CRITICAL_TEMPERATURE 94
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/* Temperature which OS will throttle CPU */
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#define PASSIVE_TEMPERATURE 85
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#endif
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef THERMAL_H
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#define THERMAL_H
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/*
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* Stoney Ridge Thermal Requirements 12 (6W)
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* TDP (W) 6
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* T die,max (°C) 95
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* T ctl,max 85
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* T die,lmt (default) 90
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* T ctl,lmt (default) 80
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*/
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/* Control TDP Settings */
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#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */
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/* Temperature which OS will shutdown at */
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#define CRITICAL_TEMPERATURE 94
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/* Temperature which OS will throttle CPU */
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#define PASSIVE_TEMPERATURE 85
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#endif
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