variants/kahlee: Add thermal ASL

Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS
thermal values in the mainboard finalize.

BUG=b:67999819

Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Marc Jones 2017-11-02 11:36:53 -06:00 committed by Marc Jones
parent c8999a7c43
commit 067031e0e1
5 changed files with 187 additions and 0 deletions

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@ -0,0 +1,90 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <variant/thermal.h>
/* Thermal Zone */
Scope (\_TZ)
{
ThermalZone (THRM)
{
/* Thermal constants for passive cooling */
Name (_TC1, 0x02)
Name (_TC2, 0x05)
/* Thermal zone polling frequency: 10 seconds */
Name (_TZP, 100)
/* Thermal sampling period for passive cooling: 2 seconds */
Name (_TSP, 20)
/* Convert from Degrees C to 1/10 Kelvin for ACPI */
Method (CTOK, 1) {
/* 10th of Degrees C */
Multiply (Arg0, 10, Local0)
/* Convert to Kelvin */
Add (Local0, 2732, Local0)
Return (Local0)
}
/* Threshold for OS to shutdown */
Method (_CRT, 0, Serialized)
{
Return (CTOK (\TCRT))
}
/* Threshold for passive cooling */
Method (_PSV, 0, Serialized)
{
Return (CTOK (\TPSV))
}
/* Processors used for passive cooling */
Method (_PSL, 0, Serialized)
{
Return (\PPKG ())
}
Method (_TMP, 0, Serialized)
{
/* Get temperature from EC in deci-kelvin */
Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
/* Critical temperature in deci-kelvin */
Store (CTOK (\TCRT), Local1)
If (LGreaterEqual (Local0, Local1)) {
Store ("CRITICAL TEMPERATURE", Debug)
Store (Local0, Debug)
/* Wait 1 second for EC to re-poll */
Sleep (1000)
/* Re-read temperature from EC */
Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
Store ("RE-READ TEMPERATURE", Debug)
Store (Local0, Debug)
}
Return (Local0)
}
/* No active fan control (_ACx) on Kahlee */
}
}

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@ -77,6 +77,9 @@ DefinitionBlock (
} /* End \_SB scope */ } /* End \_SB scope */
/* Thermal handler */
#include "acpi/thermal.asl"
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>

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@ -18,9 +18,12 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <agesawrapper.h> #include <agesawrapper.h>
#include <amd_pci_util.h> #include <amd_pci_util.h>
#include <cbmem.h>
#include <ec.h> #include <ec.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <soc/nvs.h>
#include <soc/smi.h> #include <soc/smi.h>
#include <variant/thermal.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
/*********************************************************** /***********************************************************
@ -104,7 +107,22 @@ static void kahlee_enable(device_t dev)
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
} }
static void mainboard_final(void *chip_info)
{
struct global_nvs_t *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs) {
gnvs->tmps = CTL_TDP_SENSOR_ID;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
}
}
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.init = mainboard_init, .init = mainboard_init,
.enable_dev = kahlee_enable, .enable_dev = kahlee_enable,
.final = mainboard_final,
}; };

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@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef THERMAL_H
#define THERMAL_H
/*
* Stoney Ridge Thermal Requirements 12 (6W)
* TDP (W) 6
* T die,max (°C) 95
* T ctl,max 85
* T die,lmt (default) 90
* T ctl,lmt (default) 80
*/
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 94
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 85
#endif

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@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef THERMAL_H
#define THERMAL_H
/*
* Stoney Ridge Thermal Requirements 12 (6W)
* TDP (W) 6
* T die,max (°C) 95
* T ctl,max 85
* T die,lmt (default) 90
* T ctl,lmt (default) 80
*/
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 94
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 85
#endif