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CK804/MCP55 devicetree.cb cosmetic and indentation fixes. 

Add a few more comments for the entries, and also change the devicetree.cb
files to the more compact and better readable variant with indentation level
of 2 spaces (instead of random mix of tabs and spaces).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-14 20:10:11 +00:00
parent 727edb0b32
commit 0675d5c34f
17 changed files with 2212 additions and 2245 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/mainboard/asus/a8n_e/devicetree.cb
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@ -1,14 +1,13 @@
chip northbridge/amd/amdk8/root_complex # Root complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on # APIC cluster device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_939 # Socket 939 CPU chip cpu/amd/socket_939 # CPU socket
device lapic 0 on end # APIC device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Northbridge device pci 18.0 on # Link 0 == LDT 0
# Devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 # Southbridge chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
@ -62,7 +61,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
io 0xc8 = 0x0000 io 0xc8 = 0x0000
io 0xca = 0x0500 io 0xca = 0x0500
end end
device pnp 2e.8 on # Midi port device pnp 2e.8 on # MIDI port
io 0x60 = 0x300 io 0x60 = 0x300
irq 0x70 = 10 irq 0x70 = 10
end end
@ -76,28 +75,28 @@ chip northbridge/amd/amdk8/root_complex # Root complex
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
# chip drivers/generic/generic #dimm 0-0-0 # chip drivers/generic/generic # DIMM 0-0-0
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic #dimm 0-0-1 # chip drivers/generic/generic # DIMM 0-0-1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic #dimm 0-1-0 # chip drivers/generic/generic # DIMM 0-1-0
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic #dimm 0-1-1 # chip drivers/generic/generic # DIMM 0-1-1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic #dimm 1-0-0 # chip drivers/generic/generic # DIMM 1-0-0
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic #dimm 1-0-1 # chip drivers/generic/generic # DIMM 1-0-1
# device i2c 55 on end # device i2c 55 on end
# end # end
# chip drivers/generic/generic #dimm 1-1-0 # chip drivers/generic/generic # DIMM 1-1-0
# device i2c 56 on end # device i2c 56 on end
# end # end
# chip drivers/generic/generic #dimm 1-1-1 # chip drivers/generic/generic # DIMM 1-1-1
# device i2c 57 on end # device i2c 57 on end
# end # end
end end
@ -118,6 +117,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# TODO
# register "mac_eeprom_smbus" = "3" # register "mac_eeprom_smbus" = "3"
# register "mac_eeprom_addr" = "0x51" # register "mac_eeprom_addr" = "0x51"
end end

349
src/mainboard/gigabyte/m57sli/devicetree.cb
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@ -1,174 +1,177 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_AM2 chip cpu/amd/socket_AM2 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Link 0 == LDT 0
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/ite/it8716f # Super I/O
device pnp 2e.0 on # Floppy and any LDN
# Watchdog from CLKIN (24 MHz)
irq 0x23 = 0x11
# Serial Flash (SPI only)
# 0x24 = 0x1a
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # Embedded controller
io 0x60 = 0x290
io 0x62 = 0x230
irq 0x70 = 9
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 on # PS/2 mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO, SPI flash
# Pin 84 is not GP10
irq 0x25 = 0x0
# Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
irq 0x26 = 0x43
# Pin 13 is GP35
irq 0x27 = 0x20
# Pin 70 is not GP46
# irq 0x28 = 0x0
# Pin 6,3,128,127,126 is GP63,64,65,66,67
irq 0x29 = 0x81
# Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23),
# enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22),
# pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal
# voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal
# voltage divider for VCC5V
# irq 0x2c = 0x1f
# Simple I/O base
io 0x62 = 0x800
# Serial Flash I/O (SPI only)
io 0x64 = 0x820
# Watchdog force timeout (parallel flash only)
# irq 0x71 = 0x1
# No WDT interrupt
irq 0x72 = 0x0
# GPIO pin set 1 disable internal pullup
irq 0xb8 = 0x0
# GPIO pin set 5 enable internal pullup
irq 0xbc = 0x01
# SIO pin set 1 alternate function
# irq 0xc0 = 0x0
# SIO pin set 2 mixed function
irq 0xc1 = 0x43
# SIO pin set 3 mixed function
irq 0xc2 = 0x20
# SIO pin set 4 alternate function
# irq 0xc3 = 0x0
# SIO pin set 1 input mode
# irq 0xc8 = 0x0
# SIO pin set 2 input mode
irq 0xc9 = 0x0
# SIO pin set 4 input mode
# irq 0xcb = 0x0
# Generate SMI# on EC IRQ
# irq 0xf0 = 0x10
# SMI# level trigger
# irq 0xf1 = 0x40
# HWMON alert beep pin location
irq 0xf6 = 0x28
end
device pnp 2e.8 off # MIDI
io 0x60 = 0x300
irq 0x70 = 10
end
device pnp 2e.9 off # Game port
io 0x60 = 0x220
end
device pnp 2e.a off end # Consumer IR
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI
device pci 6.1 on end # AUDIO
device pci 8.0 on end # NIC
device pci 9.0 off end # N/A
device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end
end
device pci 18.0 on end # Link 1
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
end
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 on end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io
# device pnp 0.9 off end # io
# end
end end
device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0
device pci 18.0 on # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/mcp55
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/ite/it8716f
# Floppy and any LDN
device pnp 2e.0 on
# Watchdog from CLKIN, CLKIN = 24 MHz
irq 0x23 = 0x11
# Serial Flash (SPI only)
#0x24 = 0x1a
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # EC
io 0x60 = 0x290
io 0x62 = 0x230
irq 0x70 = 9
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO, SPI flash
# pin 84 is not GP10
irq 0x25 = 0x0
# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
irq 0x26 = 0x43
# pin 13 is GP35
irq 0x27 = 0x20
# pin 70 is not GP46
#irq 0x28 = 0x0
# pin 6,3,128,127,126 is GP63,64,65,66,67
irq 0x29 = 0x81
# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
#irq 0x2c = 0x1f
# Simple I/O base
io 0x62 = 0x800
# Serial Flash I/O (SPI only)
io 0x64 = 0x820
# watch dog force timeout (parallel flash only)
#irq 0x71 = 0x1
# No WDT interrupt
irq 0x72 = 0x0
# GPIO pin set 1 disable internal pullup
irq 0xb8 = 0x0
# GPIO pin set 5 enable internal pullup
irq 0xbc = 0x01
# SIO pin set 1 alternate function
#irq 0xc0 = 0x0
# SIO pin set 2 mixed function
irq 0xc1 = 0x43
# SIO pin set 3 mixed function
irq 0xc2 = 0x20
# SIO pin set 4 alternate function
#irq 0xc3 = 0x0
# SIO pin set 1 input mode
#irq 0xc8 = 0x0
# SIO pin set 2 input mode
irq 0xc9 = 0x0
# SIO pin set 4 input mode
#irq 0xcb = 0x0
# Generate SMI# on EC IRQ
#irq 0xf0 = 0x10
# SMI# level trigger
#irq 0xf1 = 0x40
# HWMON alert beep pin location
irq 0xf6 = 0x28
end
device pnp 2e.8 off # MIDI
io 0x60 = 0x300
irq 0x70 = 10
end
device pnp 2e.9 off # GAME
io 0x60 = 0x220
end
device pnp 2e.a off end # CIR
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI
device pci 6.1 on end # AUDIO
device pci 8.0 on end # NIC
device pci 9.0 off end # N/A
device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
end #device pci 18.0
device pci 18.0 on end # Link 1
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
end # PCI domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 on end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io
# device pnp 0.9 off end # io
# end
end #root_complex

17
src/mainboard/msi/ms7135/devicetree.cb
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@ -1,14 +1,13 @@
chip northbridge/amd/amdk8/root_complex # Root complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on # APIC cluster device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_754 # Socket 754 CPU chip cpu/amd/socket_754 # CPU socket
device lapic 0 on end # APIC device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Northbridge device pci 18.0 on # Link 0 == LDT 0
# Devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 # Southbridge chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
@ -52,14 +51,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # Onboard audio (ACI) device pci 4.0 on end # Onboard audio (ACI)
device pci 4.1 off end # Onboard modem (MCI) -- not wired out device pci 4.1 off end # Onboard modem (MCI), N/A
device pci 6.0 on end # IDE device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1 device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0 device pci 8.0 on end # SATA 0
device pci 9.0 on end # PCI device pci 9.0 on end # PCI
device pci a.0 on end # NIC device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3 -- not wired out device pci b.0 off end # PCI E 3 (N/A)
device pci c.0 off end # PCI E 2 -- not wired out device pci c.0 off end # PCI E 2 (N/A)
device pci d.0 on end # PCI E 1 device pci d.0 on end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"

56
src/mainboard/msi/ms7260/devicetree.cb
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@ -1,13 +1,12 @@
chip northbridge/amd/amdk8/root_complex # Root complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on # APIC cluster device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_AM2 # CPU chip cpu/amd/socket_AM2 # CPU socket
device lapic 0 on end # APIC device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # Northbridge / mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on device pci 18.0 on # Link 0 == LDT 0
# Devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/mcp55 # Southbridge chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
@ -83,19 +82,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex
end end
# TODO: Check if the stuff below is correct / needed. # TODO: Check if the stuff below is correct / needed.
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
# PCI device SMBus address will depend on addon PCI device, # PCI device SMBus address will
# do we need to scan_smbus_bus? # depend on addon PCI device, do
# we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA Slot1 # chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic # PCIXB Slot1 # chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic # PCIXB Slot2 # chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic # PCI Slot1 # chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic # Master MCP55 PCI-E # chip drivers/generic/generic # Master MCP55 PCI-E
@ -128,7 +127,8 @@ chip northbridge/amd/amdk8/root_complex # Root complex
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# TODO: Check the two lines below. # TODO: Check the two lines below.
register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end end
@ -139,19 +139,17 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device pci 18.3 on end device pci 18.3 on end
end end
end end
# TODO
# TODO # chip drivers/generic/debug
# chip drivers/generic/debug # device pnp 0.0 off end # chip name
# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all
# device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem
# device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid
# device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr
# device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size
# device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc
# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io
# device pnp 0.8 off end # io # device pnp 0.9 off end # io
# device pnp 0.9 off end # io # end
# end
end end

353
src/mainboard/msi/ms9282/devicetree.cb
View File

@ -1,181 +1,176 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F chip cpu/amd/socket_F # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # Link 0 == LDT 0
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/winbond/w83627ehg # Super I/O
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # Serial flash
io 0x60 = 0x100
end
device pnp 2e.7 off # Game port, MIDI, GPIO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5
device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux
device i2c 70 on # 0 pca9554 1
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic # DIMM 0-0-0
device i2c 54 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 55 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 56 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 57 on end
end
end
device i2c 70 on # 0 pca9554 2
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic # DIMM 0-0-0
device i2c 54 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 55 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 56 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 57 on end
end
end
end
end
device pci 1.1 on # SM 1
chip drivers/i2c/i2cmux2 # pca9554 SMBus mux
device i2c 72 on # PCA9554 channel 1
chip drivers/i2c/adm1027 # HWM ADT7476 1
device i2c 2e on end
end
end
device i2c 72 on # PCA9545 channel 2
chip drivers/i2c/adm1027 # HWM ADT7463
device i2c 2e on end
end
end
device i2c 72 on end # PCA9545 channel 3
device i2c 72 on # PCA9545 channel 4
chip drivers/i2c/adm1027 # HWM ADT7476 2
device i2c 2e on end
end
end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # P2P
device pci 4.0 on end
end
device pci 7.0 on end # reserve
device pci 8.0 on end # MAC0
device pci 9.0 on end # MAC1
device pci a.0 on
device pci 0.0 on
device pci 4.0 on end # PCI-E LAN1
device pci 4.1 on end # PCI-E LAN2
end
end # 0x376
device pci b.0 on end # PCI E 0x374
device pci c.0 on end
device pci d.0 on # SAS
device pci 0.0 on end
end # PCI E 1 0x378
device pci e.0 on end # PCI E 0 0x375
device pci f.0 on end # PCI E 0x377, PCI-E slot
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
end end
end
device pci_domain 0 on device pci 18.0 on end # Link 1
chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end
device pci 18.0 on # northbridge device pci 18.1 on end
# devices on link 0, link 0 == LDT 0 device pci 18.2 on end
chip southbridge/nvidia/mcp55 device pci 18.3 on end
device pci 0.0 on end # HT end
device pci 1.0 on # LPC end
chip superio/winbond/w83627ehg # chip drivers/generic/debug
device pnp 2e.0 on # Floppy # device pnp 0.0 off end
io 0x60 = 0x3f0 # device pnp 0.1 off end
irq 0x70 = 6 # device pnp 0.2 off end
drq 0x74 = 2 # device pnp 0.3 off end
end # device pnp 0.4 off end
device pnp 2e.1 off # Parallel Port # device pnp 0.5 on end
io 0x60 = 0x378 # end
irq 0x70 = 7 end
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SERIAL_FALSH
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/i2c/i2cmux2 # pca9554 smbus mux
device i2c 70 on #0 pca9554 1
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 0-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 57 on end
end
end
device i2c 70 on #0 pca9554 2
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 0-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 57 on end
end
end
end
end
device pci 1.1 on # SM 1
chip drivers/i2c/i2cmux2 # pca9554 smbus mux
device i2c 72 on #pca9554 channle1
chip drivers/i2c/adm1027 #HWM ADT7476 1
device i2c 2e on end
end
end
device i2c 72 on #pca9545 channel 2
chip drivers/i2c/adm1027 #HWM ADT7463
device i2c 2e on end
end
end
device i2c 72 on end #pca9545 channel 3
device i2c 72 on #pca9545 channel 4
chip drivers/i2c/adm1027 #HWM ADT7476 2
device i2c 2e on end
end
end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on #P2P
device pci 4.0 on end
end # P2P
device pci 7.0 on end # reserve
device pci 8.0 on end # MAC0
device pci 9.0 on end # MAC1
device pci a.0 on
device pci 0.0 on
device pci 4.0 on end #pci_E lan1
device pci 4.1 on end #pci_E lan2
end
end # 0x376
device pci b.0 on end # PCI E 0x374
device pci c.0 on end
device pci d.0 on #SAS
device pci 0.0 on end
end # PCI E 1 0x378
device pci e.0 on end # PCI E 0 0x375
device pci f.0 on end #PCI E 0x377 pci_E slot
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
end
end # device pci 18.0
device pci 18.0 on end # Link 1
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end #mc0
end # pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end
# device pnp 0.1 off end
# device pnp 0.2 off end
# device pnp 0.3 off end
# device pnp 0.4 off end
# device pnp 0.5 on end
# end
end # root_complex

299
src/mainboard/msi/ms9652_fam10/devicetree.cb
View File

@ -21,152 +21,153 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdfam10 #mc0 chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on # SB on HT link 0.0 device pci 18.0 on # Link 0
chip southbridge/nvidia/mcp55 chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627ehg chip superio/winbond/w83627ehg # Super I/O
device pnp 2e.0 on # Floppy device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SERIAL_FLASH device pnp 2e.6 off # Serial flash
io 0x60 = 0x100 io 0x60 = 0x100
end end
device pnp 2e.7 off # GAME_MIDI_GIPO1 device pnp 2e.7 off # Game port, MIDI, GPIO1
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
device pnp 2e.106 off # Serial flash device pnp 2e.106 off # Serial flash
io 0x60 = 0x100 io 0x60 = 0x100
end end
device pnp 2e.207 on # MIDI device pnp 2e.207 on # MIDI
io 0x62 = 0x330 io 0x62 = 0x330
irq 0x70 = 0xa irq 0x70 = 0xa
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm 0-1-0 chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm 0-1-1 chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic #dimm 1-0-0 chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic #dimm 1-0-1 chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic #dimm 1-1-0 chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic #dimm 1-1-1 chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end # SM end
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # PCI device SMBus address will
# chip drivers/generic/generic #PCIXA Slot1 # depend on addon PCI device, do
# device i2c 50 on end # we need to scan_smbus_bus?
# end # chip drivers/generic/generic # PCIXA slot 1
# chip drivers/generic/generic #PCIXB Slot1 # device i2c 50 on end
# device i2c 51 on end # end
# end # chip drivers/generic/generic # PCIXB slot 1
# chip drivers/generic/generic #PCIXB Slot2 # device i2c 51 on end
# device i2c 52 on end # end
# end # chip drivers/generic/generic # PCIXB slot 2
# chip drivers/generic/generic #PCI Slot1 # device i2c 52 on end
# device i2c 53 on end # end
# end # chip drivers/generic/generic # PCI slot 1
# chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 53 on end
# device i2c 54 on end # end
# end # chip drivers/generic/generic # Master MCP55 PCI-E
# chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 54 on end
# device i2c 55 on end # end
# end # chip drivers/generic/generic # Slave MCP55 PCI-E
# chip drivers/generic/generic #MAC EEPROM # device i2c 55 on end
# device i2c 51 on end # end
# end # chip drivers/generic/generic # MAC EEPROM
end # SM # device i2c 51 on end
device pci 2.0 on end # USB 1.1 # end
device pci 2.1 on end # USB 2 end
device pci 4.0 on end # IDE device pci 2.0 on end # USB 1.1
device pci 5.0 on end # SATA 0 device pci 2.1 on end # USB 2
device pci 5.1 on end # SATA 1 device pci 4.0 on end # IDE
device pci 5.2 on end # SATA 2 device pci 5.0 on end # SATA 0
device pci 6.1 on end # AZA device pci 5.1 on end # SATA 1
device pci 8.0 on end # NIC device pci 5.2 on end # SATA 2
device pci 9.0 on end # NIC device pci 6.1 on end # AZA
register "ide0_enable" = "1" device pci 8.0 on end # NIC
register "sata0_enable" = "1" device pci 9.0 on end # NIC
register "sata1_enable" = "1" register "ide0_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "sata0_enable" = "1"
register "mac_eeprom_addr" = "0x51" register "sata1_enable" = "1"
end # 1: SMBus under 2e.8, 2: SM0 3: SM1
end # device pci 18.0 register "mac_eeprom_smbus" = "3"
device pci 18.0 on end # HT 1.0 register "mac_eeprom_addr" = "0x51"
device pci 18.0 on end # HT 2.0 end
device pci 18.1 on end end
device pci 18.2 on end device pci 18.0 on end # HT 1.0
device pci 18.3 on end device pci 18.0 on end # HT 2.0
device pci 18.4 on end device pci 18.1 on end
end # mc0 device pci 18.2 on end
device pci 18.3 on end
end # PCI domain device pci 18.4 on end
end
# chip drivers/generic/debug end
# device pnp 0.0 off end # chip name # chip drivers/generic/debug
# device pnp 0.1 on end # pci_regs_all # device pnp 0.0 off end # chip name
# device pnp 0.2 on end # mem # device pnp 0.1 on end # pci_regs_all
# device pnp 0.3 off end # cpuid # device pnp 0.2 on end # mem
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.3 off end # cpuid
# device pnp 0.5 off end # dual core msr # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.6 off end # cache size # device pnp 0.5 off end # dual core msr
# device pnp 0.7 off end # tsc # device pnp 0.6 off end # cache size
# device pnp 0.8 off end # io # device pnp 0.7 off end # tsc
# device pnp 0.9 off end # io # device pnp 0.8 off end # io
# end # device pnp 0.9 off end # io
end #root_complex # end
end

355
src/mainboard/nvidia/l1_2pvv/devicetree.cb
View File

@ -1,178 +1,177 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F chip cpu/amd/socket_F # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on device pci 18.0 on # Link 0 == LDT 0
# devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/mcp55 # Southbridge
chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT
device pci 0.0 on end # HT device pci 1.0 on # LPC
device pci 1.0 on # LPC chip superio/winbond/w83627ehg # Super I/O
chip superio/winbond/w83627ehg device pnp 2e.0 off # Floppy
device pnp 2e.0 off # Floppy io 0x60 = 0x3f0
io 0x60 = 0x3f0 irq 0x70 = 6
irq 0x70 = 6 drq 0x74 = 2
drq 0x74 = 2 end
end device pnp 2e.1 off # Parallel port
device pnp 2e.1 off # Parallel Port io 0x60 = 0x378
io 0x60 = 0x378 irq 0x70 = 7
irq 0x70 = 7 end
end device pnp 2e.2 on # Com1
device pnp 2e.2 on # Com1 io 0x60 = 0x3f8
io 0x60 = 0x3f8 irq 0x70 = 4
irq 0x70 = 4 end
end device pnp 2e.3 off # Com2
device pnp 2e.3 off # Com2 io 0x60 = 0x2f8
io 0x60 = 0x2f8 irq 0x70 = 3
irq 0x70 = 3 end
end device pnp 2e.5 on # PS/2 keyboard
device pnp 2e.5 on # Keyboard io 0x60 = 0x60
io 0x60 = 0x60 io 0x62 = 0x64
io 0x62 = 0x64 irq 0x70 = 1
irq 0x70 = 1 irq 0x72 = 12
irq 0x72 = 12 end
end device pnp 2e.6 off # SFI
device pnp 2e.6 off # SFI io 0x62 = 0x100
io 0x62 = 0x100 end
end device pnp 2e.7 off # GPIO, Game port, MIDI
device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220
io 0x60 = 0x220 io 0x62 = 0x300
io 0x62 = 0x300 irq 0x70 = 9
irq 0x70 = 9 end
end device pnp 2e.8 off end # WDTO PLED
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI
device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor
device pnp 2e.b on # HW Monitor io 0x60 = 0x290
io 0x60 = 0x290 irq 0x70 = 5
irq 0x70 = 5 end
end end
end end
end device pci 1.1 on # SM 0
device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0
chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end
device i2c 50 on end end
end chip drivers/generic/generic # DIMM 0-0-1
chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end
device i2c 51 on end end
end chip drivers/generic/generic # DIMM 0-1-0
chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end
device i2c 52 on end end
end chip drivers/generic/generic # DIMM 0-1-1
chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end
device i2c 53 on end end
end chip drivers/generic/generic # DIMM 1-0-0
chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end
device i2c 54 on end end
end chip drivers/generic/generic # DIMM 1-0-1
chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end
device i2c 55 on end end
end chip drivers/generic/generic # DIMM 1-1-0
chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end
device i2c 56 on end end
end chip drivers/generic/generic # DIMM 1-1-1
chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end
device i2c 57 on end end
end end
end # SM device pci 1.1 on # SM 1
device pci 1.1 on # SM 1 # PCI device SMBus address will
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # depend on addon PCI device, do
# chip drivers/generic/generic #PCIXA Slot1 # we need to scan_smbus_bus?
# device i2c 50 on end # chip drivers/generic/generic # PCIXA slot 1
# end # device i2c 50 on end
# chip drivers/generic/generic #PCIXB Slot1 # end
# device i2c 51 on end # chip drivers/generic/generic # PCIXB slot 1
# end # device i2c 51 on end
# chip drivers/generic/generic #PCIXB Slot2 # end
# device i2c 52 on end # chip drivers/generic/generic # PCIXB slot 2
# end # device i2c 52 on end
# chip drivers/generic/generic #PCI Slot1 # end
# device i2c 53 on end # chip drivers/generic/generic # PCI slot 1
# end # device i2c 53 on end
# chip drivers/generic/generic #Master MCP55 PCI-E # end
# device i2c 54 on end # chip drivers/generic/generic # Master MCP55 PCI-E
# end # device i2c 54 on end
# chip drivers/generic/generic #Slave MCP55 PCI-E # end
# device i2c 55 on end # chip drivers/generic/generic # Slave MCP55 PCI-E
# end # device i2c 55 on end
chip drivers/generic/generic #MAC EEPROM # end
device i2c 51 on end chip drivers/generic/generic # MAC EEPROM
end device i2c 51 on end
end
end # SM end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI device pci 6.0 on end # PCI
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_smbus" = "3"
end register "mac_eeprom_addr" = "0x51"
end # device pci 18.0 end
device pci 18.0 on end # Link 1 end
device pci 18.0 on device pci 18.0 on end # Link 1
# devices on link 2, link 2 == LDT 2 device pci 18.0 on # Link 2 == LDT 2
chip southbridge/nvidia/mcp55 chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on end # LPC device pci 1.0 on end # LPC
device pci 1.1 on end # SM 0 device pci 1.1 on end # SM 0
device pci 2.0 off end # USB 1.1 device pci 2.0 off end # USB 1.1
device pci 2.1 off end # USB 2 device pci 2.1 off end # USB 2
device pci 4.0 off end # IDE device pci 4.0 off end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 off end # PCI device pci 6.0 off end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1 device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_smbus" = "3"
end register "mac_eeprom_addr" = "0x51"
end # device pci 18.0 end
device pci 18.1 on end end
device pci 18.2 on end device pci 18.1 on end
device pci 18.3 on end device pci 18.2 on end
end # mc0 device pci 18.3 on end
end
end # PCI domain end
# chip drivers/generic/debug
# chip drivers/generic/debug # device pnp 0.0 off end # chip name
# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all
# device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem
# device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid
# device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr
# device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size
# device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc
# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io
# device pnp 0.8 off end # io # device pnp 0.9 off end # io
# device pnp 0.9 off end # io # end
# end end
end #root_complex

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src/mainboard/sunw/ultra40/devicetree.cb
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@ -1,152 +1,150 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_940 chip cpu/amd/socket_940 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on end
device pci 18.0 on # Link 0 == LDT 0
chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/smsc/lpc47m10x # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.3 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 off # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end
end
end
device pci 1.1 on # SM 1
# PCI device SMBus address will
# depend on addon PCI device, do
# we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end
# end
# chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end
# end
# chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end
# end
# chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end
# end
# chip drivers/generic/generic # Master CK804 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic # Slave CK804 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # ACI
device pci 4.1 off end # MCI
device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0
device pci 9.0 on end # PCI
device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end end
device pci_domain 0 on end
chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end # Link 2
device pci 18.0 on end # link 0 device pci 18.1 on end
device pci 18.0 on # link1 device pci 18.2 on end
# devices on link 0, link 0 == LDT 0 device pci 18.3 on end
chip southbridge/nvidia/ck804 end
device pci 0.0 on end # HT chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 1.0 on # LPC device pci 19.0 on end # Link 0
chip superio/smsc/lpc47m10x device pci 19.0 on # Link 1 == LDT 1
device pnp 2e.0 off # Floppy chip southbridge/nvidia/ck804 # Southbridge
io 0x60 = 0x3f0 device pci 0.0 on end # HT
irq 0x70 = 6 device pci 1.0 on end # LPC
drq 0x74 = 2 device pci 1.1 off end # SM
end device pci 2.0 off end # USB 1.1
device pnp 2e.3 off # Parallel Port device pci 2.1 off end # USB 2
io 0x60 = 0x378 device pci 4.0 off end # ACI
irq 0x70 = 7 device pci 4.1 off end # MCI
end device pci 6.0 off end # IDE
device pnp 2e.4 on # Com1 device pci 7.0 off end # SATA 1
io 0x60 = 0x3f8 device pci 8.0 off end # SATA 0
irq 0x70 = 4 device pci 9.0 off end # PCI
end device pci a.0 on end # NIC
device pnp 2e.5 off # Com2 device pci b.0 off end # PCI E 3
io 0x60 = 0x2f8 device pci c.0 off end # PCI E 2
irq 0x70 = 3 device pci d.0 off end # PCI E 1
end device pci e.0 on end # PCI E 0
device pnp 2e.7 off # Keyboard # 1: SMBus under 2e.8, 2: SM0 3: SM1
io 0x60 = 0x60 register "mac_eeprom_smbus" = "3"
io 0x62 = 0x64 register "mac_eeprom_addr" = "0x51"
irq 0x70 = 1 end
irq 0x72 = 12 end
end device pci 19.0 on end
end device pci 19.1 on end
end device pci 19.2 on end
device pci 1.1 on # SM 0 device pci 19.3 on end
chip drivers/generic/generic #dimm 0-0-0 end
device i2c 50 on end end
end end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end
end
end # SM
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master CK804 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave CK804 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # ACI
device pci 4.1 off end # MCI
device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0
device pci 9.0 on end # PCI
device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
end # device pci 18.0
device pci 18.0 on end # link 2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
chip northbridge/amd/amdk8
device pci 19.0 on end # link 0
device pci 19.0 on
# devices on link 1, link 1 == LDT 1
chip southbridge/nvidia/ck804
device pci 0.0 on end # HT
device pci 1.0 on end # LPC
device pci 1.1 off end # SM
device pci 2.0 off end # USB 1.1
device pci 2.1 off end # USB 2
device pci 4.0 off end # ACI
device pci 4.1 off end # MCI
device pci 6.0 off end # IDE
device pci 7.0 off end # SATA 1
device pci 8.0 off end # SATA 0
device pci 9.0 off end # PCI
device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end
end # device pci 19.0
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end # PCI domain
end #root_complex

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src/mainboard/supermicro/h8dme/devicetree.cb
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@ -1,139 +1,137 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F chip cpu/amd/socket_F # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0 on # Link 0 == LDT 0
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/i2c/i2cmux2
device i2c 48 off end
device i2c 49 off end
end
end
device pci 1.1 on # SM 1
# PCI device SMBus address will
# depend on addon PCI device, do
# we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end
# end
# chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end
# end
# chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end
# end
# chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end
# end
# chip drivers/generic/generic # Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic # Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI
device pci 6.0 on end
end
device pci 6.1 on end # AZA
device pci 8.0 on end # NIC
device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5
device pci 0.0 on end # NEC PCI-X
device pci 0.1 on # NEC PCI-X
device pci 4.0 on end # SCSI
device pci 4.1 on end # SCSI
end
end
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end end
device pci_domain 0 on end
chip northbridge/amd/amdk8 #mc0 device pci 18.1 on end
device pci 18.0 on end device pci 18.2 on end
device pci 18.0 on end device pci 18.3 on end
device pci 18.0 on end
# devices on link 0, link 0 == LDT 0 end
chip southbridge/nvidia/mcp55 # chip drivers/generic/debug
device pci 0.0 on end # HT # device pnp 0.0 off end # chip name
device pci 1.0 on # LPC # device pnp 0.1 on end # pci_regs_all
chip superio/winbond/w83627hf # device pnp 0.2 off end # mem
device pnp 2e.0 off # Floppy # device pnp 0.3 off end # cpuid
io 0x60 = 0x3f0 # device pnp 0.4 on end # smbus_regs_all
irq 0x70 = 6 # device pnp 0.5 off end # dual core msr
drq 0x74 = 2 # device pnp 0.6 off end # cache size
end # device pnp 0.7 off end # tsc
device pnp 2e.1 off # Parallel Port # device pnp 0.8 off end # io
io 0x60 = 0x378 # device pnp 0.9 on end # io
irq 0x70 = 7 # end
end end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/i2c/i2cmux2
device i2c 48 off end
device i2c 49 off end
end
end # SM
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI
device pci 6.0 on end
end
device pci 6.1 on end # AZA
device pci 8.0 on end # NIC
device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5
device pci 0.0 on #nec pci-x
end
device pci 0.1 on #nec pci-x
device pci 4.0 on end #scsi
device pci 4.1 on end #scsi
end
end
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
end # PCI domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io
# device pnp 0.9 on end # io
# end
end #root_complex

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@ -1,159 +1,157 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F chip cpu/amd/socket_F # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0 on # Link 0 == LDT 0
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end
end
end
device pci 1.1 on # SM 1
# PCI device SMBus address will
# depend on addon PCI device, do
# we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end
# end
# chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end
# end
# chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end
# end
# chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end
# end
# chip drivers/generic/generic # Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic # Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI
device pci 6.0 on end
end
device pci 6.1 on end # AZA
device pci 8.0 on end # NIC
device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5
device pci 0.0 on end # NEC PCI-X
device pci 0.1 on # NEC PCI-X
device pci 4.0 on end # SCSI
device pci 4.1 on end # SCSI
end
end
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end end
device pci_domain 0 on end
chip northbridge/amd/amdk8 #mc0 device pci 18.1 on end
device pci 18.0 on end device pci 18.2 on end
device pci 18.0 on end device pci 18.3 on end
device pci 18.0 on end
# devices on link 0, link 0 == LDT 0 end
chip southbridge/nvidia/mcp55 # chip drivers/generic/debug
device pci 0.0 on end # HT # device pnp 0.0 off end # chip name
device pci 1.0 on # LPC # device pnp 0.1 on end # pci_regs_all
chip superio/winbond/w83627hf # device pnp 0.2 off end # mem
device pnp 2e.0 off # Floppy # device pnp 0.3 off end # cpuid
io 0x60 = 0x3f0 # device pnp 0.4 on end # smbus_regs_all
irq 0x70 = 6 # device pnp 0.5 off end # dual core msr
drq 0x74 = 2 # device pnp 0.6 off end # cache size
end # device pnp 0.7 off end # tsc
device pnp 2e.1 off # Parallel Port # device pnp 0.8 off end # io
io 0x60 = 0x378 # device pnp 0.9 on end # io
irq 0x70 = 7 # end
end end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end
end
end # SM
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI
device pci 6.0 on end
end
device pci 6.1 on end # AZA
device pci 8.0 on end # NIC
device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5
device pci 0.0 on #nec pci-x
end
device pci 0.1 on #nec pci-x
device pci 4.0 on end #scsi
device pci 4.1 on end #scsi
end
end
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
end # PCI domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io
# device pnp 0.9 on end # io
# end
end #root_complex

326
src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
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@ -1,165 +1,163 @@
chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0 on # SB on link 2.0
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end
end
end
device pci 1.1 on # SM 1
# PCI device SMBus address will
# depend on addon PCI device, do
# we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end
# end
# chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end
# end
# chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end
# end
# chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end
# end
# chip drivers/generic/generic # Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic # Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI
device pci 6.0 on end
end
device pci 6.1 on end # AZA
device pci 8.0 on end # NIC
device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5
device pci 0.0 on end # NEC PCI-X
device pci 0.1 on # NEC PCI-X
device pci 4.0 on end # SCSI
device pci 4.1 on end # SCSI
end
end
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end end
device pci_domain 0 on end
chip northbridge/amd/amdfam10 #mc0 device pci 18.1 on end
device pci 18.0 on end device pci 18.2 on end
device pci 18.0 on end device pci 18.3 on end
device pci 18.0 on device pci 18.4 on end
# SB on link 2.0 device pci 19.0 on end
chip southbridge/nvidia/mcp55 device pci 19.1 on end
device pci 0.0 on end # HT device pci 19.2 on end
device pci 1.0 on # LPC device pci 19.3 on end
chip superio/winbond/w83627hf device pci 19.4 on end
device pnp 2e.0 off # Floppy end
io 0x60 = 0x3f0 end
irq 0x70 = 6 # chip drivers/generic/debug
drq 0x74 = 2 # device pnp 0.0 off end # chip name
end # device pnp 0.1 on end # pci_regs_all
device pnp 2e.1 off # Parallel Port # device pnp 0.2 off end # mem
io 0x60 = 0x378 # device pnp 0.3 off end # cpuid
irq 0x70 = 7 # device pnp 0.4 on end # smbus_regs_all
end # device pnp 0.5 off end # dual core msr
device pnp 2e.2 on # Com1 # device pnp 0.6 off end # cache size
io 0x60 = 0x3f8 # device pnp 0.7 off end # tsc
irq 0x70 = 4 # device pnp 0.8 off end # io
end # device pnp 0.9 on end # io
device pnp 2e.3 on # Com2 # end
io 0x60 = 0x2f8 end
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end
end
end # SM
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI
device pci 6.0 on end
end
device pci 6.1 on end # AZA
device pci 8.0 on end # NIC
device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5
device pci 0.0 on #nec pci-x
end
device pci 0.1 on #nec pci-x
device pci 4.0 on end #scsi
device pci 4.1 on end #scsi
end
end
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
device pci 19.4 on end
end # mc0
end # PCI domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io
# device pnp 0.9 on end # io
# end
end #root_complex

252
src/mainboard/supermicro/h8qme_fam10/devicetree.cb
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@ -1,128 +1,126 @@
chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0 on # SB on link 2
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # SFI
io 0x62 = 0x100
end
device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end
device pci 1.1 on # SM 1
# PCI device SMBus address will
# depend on addon PCI device, do
# we need to scan_smbus_bus?
chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end
end
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.1 off end # AZA
device pci 7.0 on
device pci 1.0 on end
end
device pci 8.0 off end
device pci 9.0 off end
device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end end
device pci_domain 0 on end
chip northbridge/amd/amdfam10 #mc0 device pci 18.1 on end
device pci 18.0 on end device pci 18.2 on end
device pci 18.0 on end device pci 18.3 on end
device pci 18.0 on device pci 18.4 on end
# SB on link 2.0 device pci 19.0 on end
chip southbridge/nvidia/mcp55 device pci 19.0 on end
device pci 0.0 on end # HT device pci 19.0 on
device pci 1.0 on # LPC chip southbridge/amd/amd8132
chip superio/winbond/w83627hf device pci 0.0 on end
device pnp 2e.0 off # Floppy device pci 0.1 on end
io 0x60 = 0x3f0 device pci 1.0 on
irq 0x70 = 6 device pci 3.0 on end
drq 0x74 = 2 device pci 3.1 on end
end end
device pnp 2e.1 off # Parallel Port device pci 1.1 on end
io 0x60 = 0x378 end
irq 0x70 = 7 end
end device pci 19.1 on end
device pnp 2e.2 on # Com1 device pci 19.2 on end
io 0x60 = 0x3f8 device pci 19.3 on end
irq 0x70 = 4 device pci 19.4 on end
end end
device pnp 2e.3 off # Com2 end
io 0x60 = 0x2f8 # chip drivers/generic/debug
irq 0x70 = 3 # device pnp 0.0 off end # chip name
end # device pnp 0.1 on end # pci_regs_all
device pnp 2e.5 on # Keyboard # device pnp 0.2 off end # mem
io 0x60 = 0x60 # device pnp 0.3 off end # cpuid
io 0x62 = 0x64 # device pnp 0.4 on end # smbus_regs_all
irq 0x70 = 1 # device pnp 0.5 off end # dual core msr
irq 0x72 = 12 # device pnp 0.6 off end # cache size
end # device pnp 0.7 off end # tsc
device pnp 2e.6 off # SFI # device pnp 0.8 off end # io
io 0x62 = 0x100 # device pnp 0.9 on end # io
end # end
device pnp 2e.7 off # GPIO_GAME_MIDI end
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
#
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.1 off end # AZA
device pci 7.0 on
device pci 1.0 on end
end
device pci 8.0 off end
device pci 9.0 off end
device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 19.0 on end
device pci 19.0 on end
device pci 19.0 on
chip southbridge/amd/amd8132
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on
device pci 3.0 on end
device pci 3.1 on end
end
device pci 1.1 on end
end #amd8132
end #device pci 19.0
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
device pci 19.4 on end
end # mc0
end # PCI domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io
# device pnp 0.9 on end # io
# end
end #root_complex

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chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_940 chip cpu/amd/socket_940 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # northbridge device pci 18.0 on # Link 0 == LDT 0
# devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge
chip southbridge/nvidia/ck804 device pci 0.0 on end # HT
device pci 0.0 on end # HT device pci 1.0 on # LPC
device pci 1.0 on # LPC chip superio/winbond/w83627hf # Super I/O
chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy
device pnp 2e.0 off # Floppy io 0x60 = 0x3f0
io 0x60 = 0x3f0 irq 0x70 = 6
irq 0x70 = 6 drq 0x74 = 2
drq 0x74 = 2 end
end device pnp 2e.1 off # Parallel port
device pnp 2e.1 off # Parallel Port io 0x60 = 0x378
io 0x60 = 0x378 irq 0x70 = 7
irq 0x70 = 7 end
end device pnp 2e.2 on # Com1
device pnp 2e.2 on # Com1 io 0x60 = 0x3f8
io 0x60 = 0x3f8 irq 0x70 = 4
irq 0x70 = 4 end
end device pnp 2e.3 off # Com2
device pnp 2e.3 off # Com2 io 0x60 = 0x2f8
io 0x60 = 0x2f8 irq 0x70 = 3
irq 0x70 = 3 end
end device pnp 2e.5 on # PS/2 keyboard & mouse
device pnp 2e.5 on # Keyboard io 0x60 = 0x60
io 0x60 = 0x60 io 0x62 = 0x64
io 0x62 = 0x64 irq 0x70 = 1
irq 0x70 = 1 irq 0x72 = 12
irq 0x72 = 12 end
end device pnp 2e.6 off # Consumer IR
device pnp 2e.6 off # CIR io 0x60 = 0x100
io 0x60 = 0x100 end
end device pnp 2e.7 off # Game port, MIDI, GPIO1
device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220
io 0x60 = 0x220 io 0x62 = 0x300
io 0x62 = 0x300 irq 0x70 = 9
irq 0x70 = 9 end
end device pnp 2e.8 off end # GPIO2
device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3
device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI
device pnp 2e.a off end # ACPI device pnp 2e.b off # Hardware monitor
device pnp 2e.b off # HW Monitor io 0x60 = 0x290
io 0x60 = 0x290 irq 0x70 = 5
irq 0x70 = 5 end
end end
end end
end device pci 1.1 on # SM 0
device pci 1.1 on # SM 0 # chip drivers/generic/generic # DIMM 0-0-0
# chip drivers/generic/generic #dimm 0-0-0 # device i2c 50 on end
# device i2c 50 on end # end
# end # chip drivers/generic/generic # DIMM 0-0-1
# chip drivers/generic/generic #dimm 0-0-1 # device i2c 51 on end
# device i2c 51 on end # end
# end # chip drivers/generic/generic # DIMM 0-1-0
# chip drivers/generic/generic #dimm 0-1-0 # device i2c 52 on end
# device i2c 52 on end # end
# end # chip drivers/generic/generic # DIMM 0-1-1
# chip drivers/generic/generic #dimm 0-1-1 # device i2c 53 on end
# device i2c 53 on end # end
# end # chip drivers/generic/generic # DIMM 1-0-0
# chip drivers/generic/generic #dimm 1-0-0 # device i2c 54 on end
# device i2c 54 on end # end
# end # chip drivers/generic/generic # DIMM 1-0-1
# chip drivers/generic/generic #dimm 1-0-1 # device i2c 55 on end
# device i2c 55 on end # end
# end # chip drivers/generic/generic # DIMM 1-1-0
# chip drivers/generic/generic #dimm 1-1-0 # device i2c 56 on end
# device i2c 56 on end # end
# end # chip drivers/generic/generic # DIMM 1-1-1
# chip drivers/generic/generic #dimm 1-1-1 # device i2c 57 on end
# device i2c 57 on end # end
# end end
end # SM # device pci 1.1 on # SM 1
# device pci 1.1 on # SM 1 # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 # device i2c 2d on end
# device i2c 2d on end # end
# end # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 # device i2c 2e on end
# device i2c 2e on end # end
# end # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN # device i2c 2a on end
# device i2c 2a on end # end
# end # chip drivers/generic/generic # Winbond HWM 0x92
# chip drivers/generic/generic # Winbond HWM 0x92 # device i2c 49 on end
# device i2c 49 on end # end
# end # chip drivers/generic/generic # Winbond HWM 0x94
# chip drivers/generic/generic # Winbond HWM 0x94 # device i2c 4a on end
# device i2c 4a on end # end
# end # end
# end #SM device pci 2.0 on end # USB 1.1
device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2
device pci 2.1 on end # USB 2 device pci 4.0 off end # ACI
device pci 4.0 off end # ACI device pci 4.1 off end # MCI
device pci 4.1 off end # MCI device pci 6.0 on end # IDE
device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1
device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0
device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI
device pci 9.0 on # PCI # chip drivers/ati/ragexl
# chip drivers/ati/ragexl device pci 7.0 on end
device pci 7.0 on end end
end device pci a.0 off end # NIC
device pci a.0 off end # NIC device pci b.0 off end # PCI E 3
device pci b.0 off end # PCI E 3 device pci c.0 off end # PCI E 2
device pci c.0 off end # PCI E 2 device pci d.0 on end # PCI E 1
device pci d.0 on end # PCI E 1 device pci e.0 on end # PCI E 0
device pci e.0 on end # PCI E 0 register "ide0_enable" = "1"
register "ide0_enable" = "1" register "ide1_enable" = "1"
register "ide1_enable" = "1" register "sata0_enable" = "1"
register "sata0_enable" = "1" register "sata1_enable" = "1"
register "sata1_enable" = "1" end
end end
end # device pci 18.0 device pci 18.0 on end # Link 1
device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2
device pci 18.0 on chip southbridge/amd/amd8131 # Southbridge
# devices on link 2, link 2 == LDT 2 device pci 0.0 on end
chip southbridge/amd/amd8131 device pci 0.1 on end
# the on/off keyword is mandatory device pci 1.0 on
device pci 0.0 on end device pci 9.0 on end
device pci 0.1 on end device pci 9.1 on end
device pci 1.0 on end
device pci 9.0 on end device pci 1.1 on end
device pci 9.1 on end end
end end
device pci 1.1 on end device pci 18.1 on end
end device pci 18.2 on end
end # device pci 18.0 device pci 18.3 on end
device pci 18.1 on end end
device pci 18.2 on end end
device pci 18.3 on end # chip drivers/generic/debug
end #mc0 # device pnp 0.0 off end # chip name
# device pnp 0.1 off end # pci_regs_all
end # pci_domain # device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# chip drivers/generic/debug # device pnp 0.4 off end # smbus_regs_all
# device pnp 0.0 off end # chip name # device pnp 0.5 off end # dual core msr
# device pnp 0.1 off end # pci_regs_all # device pnp 0.6 off end # cache size
# device pnp 0.2 off end # mem # device pnp 0.7 off end # tsc
# device pnp 0.3 off end # cpuid # device pnp 0.8 on end # hard_reset
# device pnp 0.4 off end # smbus_regs_all # end
# device pnp 0.5 off end # dual core msr end
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 on end # hard_reset
# end
end # root_complex

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chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_940 chip cpu/amd/socket_940 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # northbridge device pci 18.0 on # Link 0 == LDT 0
# devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge
chip southbridge/nvidia/ck804 device pci 0.0 on end # HT
device pci 0.0 on end # HT device pci 1.0 on # LPC
device pci 1.0 on # LPC chip superio/winbond/w83627hf # Super I/O
chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy
device pnp 2e.0 on # Floppy io 0x60 = 0x3f0
io 0x60 = 0x3f0 irq 0x70 = 6
irq 0x70 = 6 drq 0x74 = 2
drq 0x74 = 2 end
end device pnp 2e.1 on # Parallel port
device pnp 2e.1 on # Parallel Port io 0x60 = 0x378
io 0x60 = 0x378 irq 0x70 = 7
irq 0x70 = 7 drq 0x74 = 3
drq 0x74 = 3 end
end device pnp 2e.2 on # Com1
device pnp 2e.2 on # Com1 io 0x60 = 0x3f8
io 0x60 = 0x3f8 irq 0x70 = 4
irq 0x70 = 4 end
end device pnp 2e.3 off # Com2
device pnp 2e.3 off # Com2 io 0x60 = 0x2f8
io 0x60 = 0x2f8 irq 0x70 = 3
irq 0x70 = 3 end
end device pnp 2e.5 on # PS/2 keyboard & mouse
device pnp 2e.5 on # Keyboard io 0x60 = 0x60
io 0x60 = 0x60 io 0x62 = 0x64
io 0x62 = 0x64 irq 0x70 = 1
irq 0x70 = 1 irq 0x72 = 12
irq 0x72 = 12 end
end device pnp 2e.6 off # Consumer IR
device pnp 2e.6 off # CIR io 0x60 = 0x100
io 0x60 = 0x100 end
end device pnp 2e.7 off # Game port, MIDI, GPIO1
device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220
io 0x60 = 0x220 io 0x62 = 0x300
io 0x62 = 0x300 irq 0x70 = 9
irq 0x70 = 9 end
end device pnp 2e.8 off end # GPIO2
device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3
device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI
device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor
device pnp 2e.b on # HW Monitor io 0x60 = 0x290
io 0x60 = 0x290 irq 0x70 = 5
irq 0x70 = 5 end
end end
end end
end device pci 1.1 on # SM 0
device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0
chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end
device i2c 50 on end end
end chip drivers/generic/generic # DIMM 0-0-1
chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end
device i2c 51 on end end
end chip drivers/generic/generic # DIMM 0-1-0
chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end
device i2c 52 on end end
end chip drivers/generic/generic # DIMM 0-1-1
chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end
device i2c 53 on end end
end chip drivers/generic/generic # DIMM 1-0-0
chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end
device i2c 54 on end end
end chip drivers/generic/generic # DIMM 1-0-1
chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end
device i2c 55 on end end
end chip drivers/generic/generic # DIMM 1-1-0
chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end
device i2c 56 on end end
end chip drivers/generic/generic # DIMM 1-1-1
chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end
device i2c 57 on end end
end end
end # SM device pci 1.1 on # SM 1
device pci 1.1 on # SM 1 chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 device i2c 2d on end
device i2c 2d on end end
end chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 device i2c 2e on end
device i2c 2e on end end
end chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN device i2c 2a on end
device i2c 2a on end end
end chip drivers/generic/generic # Winbond HWM 0x92
chip drivers/generic/generic # Winbond HWM 0x92 device i2c 49 on end
device i2c 49 on end end
end chip drivers/generic/generic # Winbond HWM 0x94
chip drivers/generic/generic # Winbond HWM 0x94 device i2c 4a on end
device i2c 4a on end end
end end
end #SM device pci 2.0 on end # USB 1.1
device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2
device pci 2.1 on end # USB 2 device pci 4.0 off end # ACI
device pci 4.0 off end # ACI device pci 4.1 off end # MCI
device pci 4.1 off end # MCI device pci 6.0 on end # IDE
device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1
device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0
device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI
device pci 9.0 on # PCI # chip drivers/ati/ragexl
# chip drivers/ati/ragexl device pci 6.0 on end
device pci 6.0 on end # end
# end device pci 8.0 on end
device pci 8.0 on end end
end device pci a.0 off end # NIC
device pci a.0 off end # NIC device pci b.0 off end # PCI E 3
device pci b.0 off end # PCI E 3 device pci c.0 off end # PCI E 2
device pci c.0 off end # PCI E 2 device pci d.0 on end # PCI E 1
device pci d.0 on end # PCI E 1 device pci e.0 on end # PCI E 0
device pci e.0 on end # PCI E 0 register "ide0_enable" = "1"
register "ide0_enable" = "1" register "ide1_enable" = "1"
register "ide1_enable" = "1" register "sata0_enable" = "1"
register "sata0_enable" = "1" register "sata1_enable" = "1"
register "sata1_enable" = "1" end
end end
end # device pci 18.0 device pci 18.0 on end # Link 1
device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2
device pci 18.0 on chip southbridge/amd/amd8131 # Southbridge
# devices on link 2, link 2 == LDT 2 device pci 0.0 on end
chip southbridge/amd/amd8131 device pci 0.1 on end
# the on/off keyword is mandatory device pci 1.0 on
device pci 0.0 on end device pci 9.0 on end # Broadcom 5704
device pci 0.1 on end device pci 9.1 on end
device pci 1.0 on end
device pci 9.0 on end # broadcom 5704 device pci 1.1 on end
device pci 9.1 on end end
end end
device pci 1.1 on end device pci 18.1 on end
end device pci 18.2 on end
end # device pci 18.0 device pci 18.3 on end
device pci 18.1 on end end
device pci 18.2 on end end
device pci 18.3 on end # chip drivers/generic/debug
end #mc0 # device pnp 0.0 off end
# device pnp 0.1 off end
end # pci_domain # device pnp 0.2 off end
# device pnp 0.3 off end
# chip drivers/generic/debug # device pnp 0.4 off end
# device pnp 0.0 off end # device pnp 0.5 on end
# device pnp 0.1 off end # end
# device pnp 0.2 off end end
# device pnp 0.3 off end
# device pnp 0.4 off end
# device pnp 0.5 on end
# end
end # root_complex

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chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_940 chip cpu/amd/socket_940 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on # northbridge device pci 18.0 on # Link 0 == LDT 0
# devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge
chip southbridge/nvidia/ck804 device pci 0.0 on end # HT
device pci 0.0 on end # HT device pci 1.0 on # LPC
device pci 1.0 on # LPC chip superio/smsc/lpc47b397 # Super I/O
chip superio/smsc/lpc47b397 device pnp 2e.0 on # Floppy
device pnp 2e.0 on # Floppy io 0x60 = 0x3f0
io 0x60 = 0x3f0 irq 0x70 = 6
irq 0x70 = 6 drq 0x74 = 2
drq 0x74 = 2 end
end device pnp 2e.3 on # Parallel port
device pnp 2e.3 on # Parallel Port io 0x60 = 0x378
io 0x60 = 0x378 irq 0x70 = 7
irq 0x70 = 7 drq 0x74 = 4
drq 0x74 = 4 end
end device pnp 2e.4 on # Com1
device pnp 2e.4 on # Com1 io 0x60 = 0x3f8
io 0x60 = 0x3f8 irq 0x70 = 4
irq 0x70 = 4 end
end device pnp 2e.5 off # Com2
device pnp 2e.5 off # Com2 io 0x60 = 0x2f8
io 0x60 = 0x2f8 irq 0x70 = 3
irq 0x70 = 3 end
end device pnp 2e.7 on # PS/2 keyboard & mouse
device pnp 2e.7 on # Keyboard io 0x60 = 0x60
io 0x60 = 0x60 io 0x62 = 0x64
io 0x62 = 0x64 irq 0x70 = 1
irq 0x70 = 1 irq 0x72 = 12
irq 0x72 = 12 end
end device pnp 2e.8 on # Hardware monitor
device pnp 2e.8 on # HW Monitor io 0x60 = 0x480
io 0x60 = 0x480 chip drivers/generic/generic # LM95221 CPU temp
chip drivers/generic/generic # LM95221 CPU temp device i2c 2b on end
device i2c 2b on end end
end chip drivers/generic/generic # EMCT03
chip drivers/generic/generic # EMCT03 device i2c 54 on end
device i2c 54 on end end
end end
end device pnp 2e.a on # RT
device pnp 2e.a on # RT io 0x60 = 0x400
io 0x60 = 0x400 end
end end
end end
end device pci 1.1 on # SM 0
device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0
chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end
device i2c 50 on end end
end chip drivers/generic/generic # DIMM 0-0-1
chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end
device i2c 51 on end end
end chip drivers/generic/generic # DIMM 0-1-0
chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end
device i2c 52 on end end
end chip drivers/generic/generic # DIMM 0-1-1
chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end
device i2c 53 on end end
end chip drivers/generic/generic # DIMM 1-0-0
chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end
device i2c 54 on end end
end chip drivers/generic/generic # DIMM 1-0-1
chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end
device i2c 55 on end end
end chip drivers/generic/generic # DIMM 1-1-0
chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end
device i2c 56 on end end
end chip drivers/generic/generic # DIMM 1-1-1
chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end
device i2c 57 on end end
end end
end # SM device pci 1.1 on # SM 1
device pci 1.1 on # SM 1 chip drivers/generic/generic # MAC EEPROM
chip drivers/generic/generic #MAC EEPROM device i2c 51 on end
device i2c 51 on end end
end end
device pci 2.0 on end # USB 1.1
end # SM device pci 2.1 on end # USB 2
device pci 2.0 on end # USB 1.1 device pci 4.0 on end # ACI
device pci 2.1 on end # USB 2 device pci 4.1 off end # MCI
device pci 4.0 on end # ACI device pci 6.0 on end # IDE
device pci 4.1 off end # MCI device pci 7.0 on end # SATA 1
device pci 6.0 on end # IDE device pci 8.0 on end # SATA 0
device pci 7.0 on end # SATA 1 device pci 9.0 on end # PCI
device pci 8.0 on end # SATA 0 device pci a.0 on end # NIC
device pci 9.0 on end # PCI device pci b.0 off end # PCI E 3
device pci a.0 on end # NIC device pci c.0 off end # PCI E 2
device pci b.0 off end # PCI E 3 device pci d.0 off end # PCI E 1
device pci c.0 off end # PCI E 2 device pci e.0 on end # PCI E 0
device pci d.0 off end # PCI E 1 register "ide0_enable" = "1"
device pci e.0 on end # PCI E 0 register "ide1_enable" = "1"
register "ide0_enable" = "1" register "sata0_enable" = "1"
register "ide1_enable" = "1" register "sata1_enable" = "1"
register "sata0_enable" = "1" # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "sata1_enable" = "1" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51"
register "mac_eeprom_addr" = "0x51" end
end end
end # device pci 18.0 device pci 18.0 on end # Link 1
device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2
device pci 18.0 on chip southbridge/amd/amd8131 # Southbridge
# devices on link 2, link 2 == LDT 2 device pci 0.0 on end
chip southbridge/amd/amd8131 device pci 0.1 on end
# the on/off keyword is mandatory device pci 1.0 on
device pci 0.0 on end device pci 6.0 on end # LSI SCSI
device pci 0.1 on end device pci 6.1 on end
device pci 1.0 on end
device pci 6.0 on end # lsi scsi device pci 1.1 on end
device pci 6.1 on end end
end end
device pci 1.1 on end device pci 18.1 on end
end device pci 18.2 on end
end # device pci 18.0 device pci 18.3 on end
device pci 18.1 on end end
device pci 18.2 on end chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.3 on end device pci 19.0 on # Link 0 == LDT 0
end #mc0 chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT
chip northbridge/amd/amdk8 device pci 1.0 on end # LPC
device pci 19.0 on # northbridge device pci 1.1 off end # SM
# devices on link 0, link 0 == LDT 0 device pci 2.0 off end # USB 1.1
chip southbridge/nvidia/ck804 device pci 2.1 off end # USB 2
device pci 0.0 on end # HT device pci 4.0 off end # ACI
device pci 1.0 on end # LPC device pci 4.1 off end # MCI
device pci 1.1 off end # SM device pci 6.0 off end # IDE
device pci 2.0 off end # USB 1.1 device pci 7.0 off end # SATA 1
device pci 2.1 off end # USB 2 device pci 8.0 off end # SATA 0
device pci 4.0 off end # ACI device pci 9.0 off end # PCI
device pci 4.1 off end # MCI device pci a.0 on end # NIC
device pci 6.0 off end # IDE device pci b.0 off end # PCI E 3
device pci 7.0 off end # SATA 1 device pci c.0 off end # PCI E 2
device pci 8.0 off end # SATA 0 device pci d.0 off end # PCI E 1
device pci 9.0 off end # PCI device pci e.0 on end # PCI E 0
device pci a.0 on end # NIC # 1: SMBus under 2e.8, 2: SM0 3: SM1
device pci b.0 off end # PCI E 3 register "mac_eeprom_smbus" = "3"
device pci c.0 off end # PCI E 2 register "mac_eeprom_addr" = "0x51"
device pci d.0 off end # PCI E 1 end
device pci e.0 on end # PCI E 0 end
register "mac_eeprom_smbus" = "3" device pci 19.0 on end
register "mac_eeprom_addr" = "0x51" device pci 19.0 on end
end device pci 19.1 on end
end # device pci 19.0 device pci 19.2 on end
device pci 19.3 on end
device pci 19.0 on end end
device pci 19.0 on end end
device pci 19.1 on end # chip drivers/generic/debug
device pci 19.2 on end # device pnp 0.0 off end # chip name
device pci 19.3 on end # device pnp 0.1 off end # pci_regs_all
end # device pnp 0.2 off end # mem
end # PCI domain # device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# chip drivers/generic/debug # device pnp 0.5 off end # dual core msr
# device pnp 0.0 off end # chip name # device pnp 0.6 off end # cache size
# device pnp 0.1 off end # pci_regs_all # device pnp 0.7 off end # tsc
# device pnp 0.2 off end # mem # end
# device pnp 0.3 off end # cpuid end
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end # root_complex

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src/mainboard/tyan/s2912/devicetree.cb
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@ -1,150 +1,149 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F chip cpu/amd/socket_F # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on device pci 18.0 on
# devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/mcp55 # Southbridge
chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT
device pci 0.0 on end # HT device pci 1.0 on # LPC
device pci 1.0 on # LPC chip superio/winbond/w83627hf # Super I/O
chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy
device pnp 2e.0 off # Floppy io 0x60 = 0x3f0
io 0x60 = 0x3f0 irq 0x70 = 6
irq 0x70 = 6 drq 0x74 = 2
drq 0x74 = 2 end
end device pnp 2e.1 off # Parallel port
device pnp 2e.1 off # Parallel Port io 0x60 = 0x378
io 0x60 = 0x378 irq 0x70 = 7
irq 0x70 = 7 end
end device pnp 2e.2 on # Com1
device pnp 2e.2 on # Com1 io 0x60 = 0x3f8
io 0x60 = 0x3f8 irq 0x70 = 4
irq 0x70 = 4 end
end device pnp 2e.3 on # Com2
device pnp 2e.3 on # Com2 io 0x60 = 0x2f8
io 0x60 = 0x2f8 irq 0x70 = 3
irq 0x70 = 3 end
end device pnp 2e.5 on # PS/2 keyboard
device pnp 2e.5 on # Keyboard io 0x60 = 0x60
io 0x60 = 0x60 io 0x62 = 0x64
io 0x62 = 0x64 irq 0x70 = 1
irq 0x70 = 1 irq 0x72 = 12
irq 0x72 = 12 end
end device pnp 2e.6 off # SFI
device pnp 2e.6 off # SFI io 0x62 = 0x100
io 0x62 = 0x100 end
end device pnp 2e.7 off # GPIO, game port, MIDI
device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220
io 0x60 = 0x220 io 0x62 = 0x300
io 0x62 = 0x300 irq 0x70 = 9
irq 0x70 = 9 end
end device pnp 2e.8 off end # WDTO PLED
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI
device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor
device pnp 2e.b on # HW Monitor io 0x60 = 0x290
io 0x60 = 0x290 irq 0x70 = 5
irq 0x70 = 5 end
end end
end end
end device pci 1.1 on # SM 0
device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0
chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end
device i2c 50 on end end
end chip drivers/generic/generic # DIMM 0-0-1
chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end
device i2c 51 on end end
end chip drivers/generic/generic # DIMM 0-1-0
chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end
device i2c 52 on end end
end chip drivers/generic/generic # DIMM 0-1-1
chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end
device i2c 53 on end end
end chip drivers/generic/generic # DIMM 1-0-0
chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end
device i2c 54 on end end
end chip drivers/generic/generic # DIMM 1-0-1
chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end
device i2c 55 on end end
end chip drivers/generic/generic # DIMM 1-1-0
chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end
device i2c 56 on end end
end chip drivers/generic/generic # DIMM 1-1-1
chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end
device i2c 57 on end end
end end
end # SM device pci 1.1 on # SM 1
device pci 1.1 on # SM 1 # PCI device SMBus address will
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # depend on addon PCI device, do
# chip drivers/generic/generic #PCIXA Slot1 # we need to scan_smbus_bus?
# device i2c 50 on end # chip drivers/generic/generic # PCIXA slot 1
# end # device i2c 50 on end
# chip drivers/generic/generic #PCIXB Slot1 # end
# device i2c 51 on end # chip drivers/generic/generic # PCIXB slot 1
# end # device i2c 51 on end
# chip drivers/generic/generic #PCIXB Slot2 # end
# device i2c 52 on end # chip drivers/generic/generic # PCIXB slot 2
# end # device i2c 52 on end
# chip drivers/generic/generic #PCI Slot1 # end
# device i2c 53 on end # chip drivers/generic/generic # PCI slot 1
# end # device i2c 53 on end
# chip drivers/generic/generic #Master MCP55 PCI-E # end
# device i2c 54 on end # chip drivers/generic/generic # Master MCP55 PCI-E
# end # device i2c 54 on end
# chip drivers/generic/generic #Slave MCP55 PCI-E # end
# device i2c 55 on end # chip drivers/generic/generic # Slave MCP55 PCI-E
# end # device i2c 55 on end
chip drivers/generic/generic #MAC EEPROM # end
device i2c 51 on end chip drivers/generic/generic # MAC EEPROM
end device i2c 51 on end
end
end # SM end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI device pci 6.0 on end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_smbus" = "3"
end register "mac_eeprom_addr" = "0x51"
end # device pci 18.0 end
device pci 18.1 on end end
device pci 18.2 on end device pci 18.1 on end
device pci 18.3 on end device pci 18.2 on end
end # mc0 device pci 18.3 on end
end
end # PCI domain end
# chip drivers/generic/debug
# chip drivers/generic/debug # device pnp 0.0 off end # chip name
# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all
# device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem
# device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid
# device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr
# device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size
# device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc
# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io
# device pnp 0.8 off end # io # device pnp 0.9 off end # io
# device pnp 0.9 off end # io # end
# end end
end #root_complex

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src/mainboard/tyan/s2912_fam10/devicetree.cb
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chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10/root_complex # Root complex
device lapic_cluster 0 on device lapic_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end device lapic 0 on end # Local APIC of the CPU
end end
end end
device pci_domain 0 on device pci_domain 0 on # PCI domain
chip northbridge/amd/amdfam10 #mc0 chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on device pci 18.0 on # SB on link 2
# SB on link 2.0. chip southbridge/nvidia/mcp55 # Southbridge
chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT
device pci 0.0 on end # HT device pci 1.0 on # LPC
device pci 1.0 on # LPC chip superio/winbond/w83627hf # Super I/O
chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy
device pnp 2e.0 off # Floppy io 0x60 = 0x3f0
io 0x60 = 0x3f0 irq 0x70 = 6
irq 0x70 = 6 drq 0x74 = 2
drq 0x74 = 2 end
end device pnp 2e.1 off # Parallel port
device pnp 2e.1 off # Parallel Port io 0x60 = 0x378
io 0x60 = 0x378 irq 0x70 = 7
irq 0x70 = 7 end
end device pnp 2e.2 on # Com1
device pnp 2e.2 on # Com1 io 0x60 = 0x3f8
io 0x60 = 0x3f8 irq 0x70 = 4
irq 0x70 = 4 end
end device pnp 2e.3 on # Com2
device pnp 2e.3 on # Com2 io 0x60 = 0x2f8
io 0x60 = 0x2f8 irq 0x70 = 3
irq 0x70 = 3 end
end device pnp 2e.5 on # PS/2 keyboard
device pnp 2e.5 on # Keyboard io 0x60 = 0x60
io 0x60 = 0x60 io 0x62 = 0x64
io 0x62 = 0x64 irq 0x70 = 1
irq 0x70 = 1 irq 0x72 = 12
irq 0x72 = 12 end
end device pnp 2e.6 off # SFI
device pnp 2e.6 off # SFI io 0x62 = 0x100
io 0x62 = 0x100 end
end device pnp 2e.7 off # GPIO, game port, MIDI
device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220
io 0x60 = 0x220 io 0x62 = 0x300
io 0x62 = 0x300 irq 0x70 = 9
irq 0x70 = 9 end
end device pnp 2e.8 off end # WDTO PLED
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI
device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor
device pnp 2e.b on # HW Monitor io 0x60 = 0x290
io 0x60 = 0x290 irq 0x70 = 5
irq 0x70 = 5 end
end end
end end
end device pci 1.1 on # SM 0
device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0
chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end
device i2c 50 on end end
end chip drivers/generic/generic # DIMM 0-0-1
chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end
device i2c 51 on end end
end chip drivers/generic/generic # DIMM 0-1-0
chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end
device i2c 52 on end end
end chip drivers/generic/generic # DIMM 0-1-1
chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end
device i2c 53 on end end
end chip drivers/generic/generic # DIMM 1-0-0
chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end
device i2c 54 on end end
end chip drivers/generic/generic # DIMM 1-0-1
chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end
device i2c 55 on end end
end chip drivers/generic/generic # DIMM 1-1-0
chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end
device i2c 56 on end end
end chip drivers/generic/generic # DIMM 1-1-1
chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end
device i2c 57 on end end
end end
end # SM device pci 1.1 on # SM 1
device pci 1.1 on # SM 1 # PCI device SMBus address will
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # depend on addon PCI device, do
# chip drivers/generic/generic #PCIXA Slot1 # we need to scan_smbus_bus?
# device i2c 50 on end # chip drivers/generic/generic # PCIXA slot 1
# end # device i2c 50 on end
# chip drivers/generic/generic #PCIXB Slot1 # end
# device i2c 51 on end # chip drivers/generic/generic # PCIXB slot 1
# end # device i2c 51 on end
# chip drivers/generic/generic #PCIXB Slot2 # end
# device i2c 52 on end # chip drivers/generic/generic # PCIXB slot 2
# end # device i2c 52 on end
# chip drivers/generic/generic #PCI Slot1 # end
# device i2c 53 on end # chip drivers/generic/generic # PCI slot 1
# end # device i2c 53 on end
# chip drivers/generic/generic #Master MCP55 PCI-E # end
# device i2c 54 on end # chip drivers/generic/generic # Master MCP55 PCI-E
# end # device i2c 54 on end
# chip drivers/generic/generic #Slave MCP55 PCI-E # end
# device i2c 55 on end # chip drivers/generic/generic # Slave MCP55 PCI-E
# end # device i2c 55 on end
chip drivers/generic/generic #MAC EEPROM # end
device i2c 51 on end chip drivers/generic/generic # MAC EEPROM
end device i2c 51 on end
end
end # SM end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on device pci 6.0 on # PCI
device pci 4.0 on end device pci 4.0 on end
end # PCI end
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_smbus" = "3"
end register "mac_eeprom_addr" = "0x51"
end # device pci 18.0 end
device pci 18.1 on end end
device pci 18.2 on end device pci 18.1 on end
device pci 18.3 on end device pci 18.2 on end
device pci 18.4 on end device pci 18.3 on end
end # mc0 device pci 18.4 on end
end
end # PCI domain end
# chip drivers/generic/debug
# chip drivers/generic/debug # device pnp 0.0 off end # chip name
# device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all
# device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem
# device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid
# device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr
# device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size
# device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc
# device pnp 0.7 off end # tsc # device pnp 0.8 off end # io
# device pnp 0.8 off end # io # device pnp 0.9 off end # io
# device pnp 0.9 off end # io # end
# end end
end #root_complex