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amd/cezanne: Add telemetry setting to UPD 

Add telemetry setting to UPD, the value comes from the SDLE testing.

BUG=b:182754399
TEST=Build & Boot guybrush

Cq-Depend: chrome-internal:3787638
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2021-04-29 00:11:01 +08:00 committed by Felix Held
parent ca084b8db2
commit 0679392177
3 changed files with 23 additions and 2 deletions
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7
src/soc/amd/cezanne/chip.h
View File

@ -68,6 +68,13 @@ struct soc_amd_cezanne_config {
uint8_t cppc_epp_max_range;
uint8_t cppc_epp_min_range;
uint8_t cppc_preferred_cores;
/* telemetry settings */
uint32_t telemetry_vddcrvddfull_scale_current_mA;
uint32_t telemetry_vddcrvddoffset;
uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset;
};
#endif /* CEZANNE_CHIP_H */

10
src/soc/amd/cezanne/fsp_m_params.c
View File

@ -118,5 +118,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* S0i3 enable */
mcfg->s0i3_enable = config->s0ix_enable;
/* voltage regulator telemetry settings */
mcfg->telemetry_vddcrvddfull_scale_current =
config->telemetry_vddcrvddfull_scale_current_mA;
mcfg->telemetry_vddcrvddoffset =
config->telemetry_vddcrvddoffset;
mcfg->telemetry_vddcrsocfull_scale_current =
config->telemetry_vddcrsocfull_scale_current_mA;
mcfg->telemetry_vddcrsocOffset =
config->telemetry_vddcrsocoffset;
fsp_fill_pcie_ddi_descriptors(mcfg);
}

8
src/vendorcode/amd/fsp/cezanne/FspmUpd.h
View File

@ -102,8 +102,12 @@ typedef struct __packed {
/** Offset 0x04A4**/ uint8_t fch_ioapic_id;
/** Offset 0x04A5**/ uint8_t sata_enable;
/** Offset 0x04A6**/ uint8_t fch_reserved[32];
/** Offset 0x04A7**/ uint8_t s0i3_enable;
/** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[57];
/** Offset 0x04C6**/ uint8_t s0i3_enable;
/** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current;
/** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset;
/** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current;
/** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset;
/** Offset 0x04D7**/ uint8_t UnusedUpdSpace0[41];
/** Offset 0x0500**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;