GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: Unify the definition of TCO registers 

Move the definition of the TCO registers used in most boards to a
separate file and use it consistently. Do not unify TCO for older
incompatible platforms.

BUG=b:314260167
TEST=none

Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
This commit is contained in:
Marek Maslanka 2024-01-17 14:57:36 +00:00 committed by Felix Held
parent 33387eb23d
commit 06798cd53f
11 changed files with 64 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/apollolake/elog.c
View File

@ -76,7 +76,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
ps->tco1_sts & TCO_TIMEOUT)
ps->tco1_sts & TCO1_STS_TIMEOUT)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */

14
src/soc/intel/apollolake/include/soc/smbus.h
View File

@ -3,19 +3,7 @@
#ifndef _SOC_APOLLOLAKE_SMBUS_H_
#define _SOC_APOLLOLAKE_SMBUS_H_
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO2_CNT 0x0A
#define TCO_INTRD_SEL_MASK (3 << 1)
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
#include <soc/intel/common/tco.h>
#define SMBUS_SLAVE_ADDR 0x24

8
src/soc/intel/common/block/smbus/tco.c
View File

@ -56,7 +56,7 @@ void tco_lockdown(void)
/* TCO Lock down */
tcocnt = tco_read_reg(TCO1_CNT);
tcocnt |= TCO_LOCK;
tcocnt |= TCO1_LOCK;
tco_write_reg(TCO1_CNT, tcocnt);
}
@ -83,7 +83,7 @@ static void tco_timer_disable(void)
/* Program TCO timer halt */
tcocnt = tco_read_reg(TCO1_CNT);
tcocnt |= TCO_TMR_HLT;
tcocnt |= TCO1_TMR_HLT;
tco_write_reg(TCO1_CNT, tcocnt);
}
@ -94,8 +94,8 @@ static void tco_intruder_smi_enable(void)
/* Make TCO issue an SMI on INTRD_DET assertion */
tcocnt = tco_read_reg(TCO2_CNT);
tcocnt &= ~TCO_INTRD_SEL_MASK;
tcocnt |= TCO_INTRD_SEL_SMI;
tcocnt &= ~TCO2_INTRD_SEL_MASK;
tcocnt |= TCO2_INTRD_SEL_SMI;
tco_write_reg(TCO2_CNT, tcocnt);
}

4
src/soc/intel/common/block/smm/smihandler.c
View File

@ -460,12 +460,12 @@ void smihandler_southbridge_tco(
if (!tco_sts)
return;
if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
if (tco_sts & TCO1_STS_TIMEOUT) { /* TIMEOUT */
/* Handle TCO timeout */
printk(BIOS_DEBUG, "TCO Timeout.\n");
}
if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */
if (tco_sts & (TCO2_INTRD_DET << 16)) { /* INTRUDER# assertion */
/*
* Handle intrusion event
* If we ever get here, probably the case has been opened.

14
src/soc/intel/common/pch/include/intelpch/smbus.h
View File

@ -3,19 +3,7 @@
#ifndef _INTELPCH_SMBUS_H_
#define _INTELPCH_SMBUS_H_
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO2_CNT 0x0A
#define TCO_INTRD_SEL_MASK (3 << 1)
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
#include <soc/intel/common/tco.h>
/*
* Default slave address value for PCH. This value is set to match default

47
src/soc/intel/common/tco.h Normal file
View File

@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _INTELPCH_TCO_H_
#define _INTELPCH_TCO_H_
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO_RLD 0x00
#define TCO_DAT_IN 0x02
#define TCO_DAT_OUT 0x03
#define TCO1_STS 0x04
#define TCO1_STS_TCO_SLVSEL (1 << 13)
#define TCO1_STS_CPUSERR (1 << 12)
#define TCO1_STS_CPUSMI (1 << 10)
#define TCO1_STS_CPUSCI (1 << 9)
#define TCO1_STS_BIOSWR (1 << 8)
#define TCO1_STS_NEWCENTURY (1 << 7)
#define TCO1_STS_TIMEOUT (1 << 3)
#define TCO1_STS_TCO_INT (1 << 2)
#define TCO1_STS_OS_TCO_SMI (1 << 1)
#define TCO1_STS_NMI2SMI (1 << 0)
#define TCO2_STS 0x06
#define TCO2_STS_SMLINK_SLAVE_SMI (1 << 2)
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO2_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO1_LOCK (1 << 12)
#define TCO1_TMR_HLT (1 << 11)
#define TCO1_NMI2SMI_EN (1 << 9)
#define TCO1_NMI_NOW (1 << 8)
#define TCO2_CNT 0x0A
#define TCO2_OS_POLICY_MASK (3 << 4)
#define TCO2_OS_POLICY_SHUTDOWN (1 << 4)
#define TCO2_OS_POLICY_DONOT_LOAD (1 << 5)
#define TCO2_SMB_ALERT_DISABLE (1 << 3)
#define TCO2_INTRD_SEL_MASK (3 << 1)
#define TCO2_INTRD_SEL_SMI (1 << 2)
#define TCO2_INTRD_SEL_INT (1 << 1)
#define TCO_MESSAGE1 0x0C
#define TCO_MESSAGE2 0x0D
#define TCO_WDSTATUS 0x0E
#define TCO_LEGACY_ELIM 0x10
#define TCO_IRQ12_CAUSE (1 << 1)
#define TCO_IRQ1_CAUSE (1 << 0)
#define TCO_TMR 0x12
#define TCO_TMR_MASK 0x3FF
#endif

25
src/soc/intel/denverton_ns/include/soc/pmc.h
View File

@ -3,6 +3,8 @@
#ifndef _DENVERTON_NS_PMC_H_
#define _DENVERTON_NS_PMC_H_
#include <soc/intel/common/tco.h>
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PMC_ACPI_BASE 0x40 /* IO BAR */
#define MASK_PMC_ACPI_BASE 0xfffc
@ -214,29 +216,6 @@
#define SWGPE_EN (1 << 2)
#define HOT_PLUG_EN (1 << 1)
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO_RLD 0x00
#define TCO1_STS 0x04
#define TCO1_STS_TCO_SLVSEL (1 << 13)
#define TCO1_STS_CPUSERR (1 << 12)
#define TCO1_STS_CPUSMI (1 << 10)
#define TCO1_STS_CPUSCI (1 << 9)
#define TCO1_STS_BIOSWR (1 << 8)
#define TCO1_STS_NEWCENTURY (1 << 7)
#define TCO1_STS_TIMEOUT (1 << 3)
#define TCO1_STS_TCO_INT (1 << 2)
#define TCO1_STS_OS_TCO_SMI (1 << 1)
#define TCO1_STS_NMI2SMI (1 << 0)
#define TCO2_STS 0x06
#define TCO2_STS_SMLINK_SLAVE_SMI 0x04
#define TCO2_STS_SECOND_TO 0x02
#define TCO2_STS_INTRD_DET 0x01
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO2_CNT 0x0a
#define TCO_TMR 0x12
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x10
#define GPIO_GPE_CFG 0x120

2
src/soc/intel/denverton_ns/romstage.c
View File

@ -110,7 +110,7 @@ static void early_tco_init(void)
/* Halt the TCO timer */
uint16_t reg16 = inw(tco_base + TCO1_CNT);
reg16 |= TCO_TMR_HLT;
reg16 |= TCO1_TMR_HLT;
outw(reg16, tco_base + TCO1_CNT);
/* Clear the Second TCO status bit */

14
src/soc/intel/xeon_sp/include/soc/smbus.h
View File

@ -3,19 +3,7 @@
#ifndef _SOC_SMBUS_H_
#define _SOC_SMBUS_H_
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO2_CNT 0x0A
#define TCO_INTRD_SEL_MASK (3 << 1)
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
#include <soc/intel/common/tco.h>
/* SMBus I/O bits. */
#define SMBUS_SLAVE_ADDR 0x24

9
src/southbridge/intel/common/tco.h
View File

@ -10,13 +10,8 @@
#undef TCO1_CNT
#endif
#include <soc/intel/common/tco.h>
#define PMBASE_TCO_OFFSET 0x60
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO1_CNT 0x08
#define TCO_TMR_HLT (1 << 11)
#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */

4
src/southbridge/intel/common/watchdog.c
View File

@ -27,11 +27,11 @@ void watchdog_off(void)
/* Disable the watchdog timer. */
value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
value |= TCO_TMR_HLT;
value |= TCO1_TMR_HLT;
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
/* Clear TCO timeout status. */
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_STS_TIMEOUT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");