soc/intel: Unify the definition of TCO registers
Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
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@ -76,7 +76,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
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/* TCO Timeout */
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if (ps->prev_sleep_state != ACPI_S3 &&
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ps->tco1_sts & TCO_TIMEOUT)
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ps->tco1_sts & TCO1_STS_TIMEOUT)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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@ -3,19 +3,7 @@
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#ifndef _SOC_APOLLOLAKE_SMBUS_H_
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#define _SOC_APOLLOLAKE_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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#include <soc/intel/common/tco.h>
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#define SMBUS_SLAVE_ADDR 0x24
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@ -56,7 +56,7 @@ void tco_lockdown(void)
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/* TCO Lock down */
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tcocnt = tco_read_reg(TCO1_CNT);
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tcocnt |= TCO_LOCK;
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tcocnt |= TCO1_LOCK;
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tco_write_reg(TCO1_CNT, tcocnt);
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}
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@ -83,7 +83,7 @@ static void tco_timer_disable(void)
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/* Program TCO timer halt */
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tcocnt = tco_read_reg(TCO1_CNT);
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tcocnt |= TCO_TMR_HLT;
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tcocnt |= TCO1_TMR_HLT;
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tco_write_reg(TCO1_CNT, tcocnt);
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}
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@ -94,8 +94,8 @@ static void tco_intruder_smi_enable(void)
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/* Make TCO issue an SMI on INTRD_DET assertion */
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tcocnt = tco_read_reg(TCO2_CNT);
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tcocnt &= ~TCO_INTRD_SEL_MASK;
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tcocnt |= TCO_INTRD_SEL_SMI;
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tcocnt &= ~TCO2_INTRD_SEL_MASK;
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tcocnt |= TCO2_INTRD_SEL_SMI;
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tco_write_reg(TCO2_CNT, tcocnt);
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}
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@ -460,12 +460,12 @@ void smihandler_southbridge_tco(
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if (!tco_sts)
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return;
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if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
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if (tco_sts & TCO1_STS_TIMEOUT) { /* TIMEOUT */
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/* Handle TCO timeout */
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printk(BIOS_DEBUG, "TCO Timeout.\n");
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}
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if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */
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if (tco_sts & (TCO2_INTRD_DET << 16)) { /* INTRUDER# assertion */
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/*
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* Handle intrusion event
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* If we ever get here, probably the case has been opened.
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@ -3,19 +3,7 @@
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#ifndef _INTELPCH_SMBUS_H_
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#define _INTELPCH_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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#include <soc/intel/common/tco.h>
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/*
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* Default slave address value for PCH. This value is set to match default
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@ -0,0 +1,47 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _INTELPCH_TCO_H_
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#define _INTELPCH_TCO_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO_RLD 0x00
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#define TCO_DAT_IN 0x02
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#define TCO_DAT_OUT 0x03
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#define TCO1_STS 0x04
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#define TCO1_STS_TCO_SLVSEL (1 << 13)
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#define TCO1_STS_CPUSERR (1 << 12)
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#define TCO1_STS_CPUSMI (1 << 10)
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#define TCO1_STS_CPUSCI (1 << 9)
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#define TCO1_STS_BIOSWR (1 << 8)
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#define TCO1_STS_NEWCENTURY (1 << 7)
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#define TCO1_STS_TIMEOUT (1 << 3)
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#define TCO1_STS_TCO_INT (1 << 2)
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#define TCO1_STS_OS_TCO_SMI (1 << 1)
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#define TCO1_STS_NMI2SMI (1 << 0)
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#define TCO2_STS 0x06
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#define TCO2_STS_SMLINK_SLAVE_SMI (1 << 2)
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define TCO2_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO1_LOCK (1 << 12)
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#define TCO1_TMR_HLT (1 << 11)
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#define TCO1_NMI2SMI_EN (1 << 9)
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#define TCO1_NMI_NOW (1 << 8)
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#define TCO2_CNT 0x0A
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#define TCO2_OS_POLICY_MASK (3 << 4)
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#define TCO2_OS_POLICY_SHUTDOWN (1 << 4)
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#define TCO2_OS_POLICY_DONOT_LOAD (1 << 5)
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#define TCO2_SMB_ALERT_DISABLE (1 << 3)
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#define TCO2_INTRD_SEL_MASK (3 << 1)
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#define TCO2_INTRD_SEL_SMI (1 << 2)
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#define TCO2_INTRD_SEL_INT (1 << 1)
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#define TCO_MESSAGE1 0x0C
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#define TCO_MESSAGE2 0x0D
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#define TCO_WDSTATUS 0x0E
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#define TCO_LEGACY_ELIM 0x10
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#define TCO_IRQ12_CAUSE (1 << 1)
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#define TCO_IRQ1_CAUSE (1 << 0)
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#define TCO_TMR 0x12
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#define TCO_TMR_MASK 0x3FF
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#endif
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@ -3,6 +3,8 @@
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#ifndef _DENVERTON_NS_PMC_H_
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#define _DENVERTON_NS_PMC_H_
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#include <soc/intel/common/tco.h>
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/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
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#define PMC_ACPI_BASE 0x40 /* IO BAR */
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#define MASK_PMC_ACPI_BASE 0xfffc
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@ -214,29 +216,6 @@
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#define SWGPE_EN (1 << 2)
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#define HOT_PLUG_EN (1 << 1)
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO_RLD 0x00
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#define TCO1_STS 0x04
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#define TCO1_STS_TCO_SLVSEL (1 << 13)
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#define TCO1_STS_CPUSERR (1 << 12)
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#define TCO1_STS_CPUSMI (1 << 10)
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#define TCO1_STS_CPUSCI (1 << 9)
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#define TCO1_STS_BIOSWR (1 << 8)
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#define TCO1_STS_NEWCENTURY (1 << 7)
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#define TCO1_STS_TIMEOUT (1 << 3)
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#define TCO1_STS_TCO_INT (1 << 2)
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#define TCO1_STS_OS_TCO_SMI (1 << 1)
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#define TCO1_STS_NMI2SMI (1 << 0)
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#define TCO2_STS 0x06
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#define TCO2_STS_SMLINK_SLAVE_SMI 0x04
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#define TCO2_STS_SECOND_TO 0x02
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#define TCO2_STS_INTRD_DET 0x01
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0a
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#define TCO_TMR 0x12
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/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
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#define PRSTS 0x10
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#define GPIO_GPE_CFG 0x120
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@ -110,7 +110,7 @@ static void early_tco_init(void)
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/* Halt the TCO timer */
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uint16_t reg16 = inw(tco_base + TCO1_CNT);
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reg16 |= TCO_TMR_HLT;
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reg16 |= TCO1_TMR_HLT;
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outw(reg16, tco_base + TCO1_CNT);
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/* Clear the Second TCO status bit */
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@ -3,19 +3,7 @@
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#ifndef _SOC_SMBUS_H_
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#define _SOC_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define TCO_INTRD_DET (1 << 0)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO2_CNT 0x0A
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#define TCO_INTRD_SEL_MASK (3 << 1)
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#define TCO_INTRD_SEL_SMI (1 << 2)
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#define TCO_INTRD_SEL_INT (1 << 1)
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#include <soc/intel/common/tco.h>
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/* SMBus I/O bits. */
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#define SMBUS_SLAVE_ADDR 0x24
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@ -10,13 +10,8 @@
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#undef TCO1_CNT
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#endif
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#include <soc/intel/common/tco.h>
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#define PMBASE_TCO_OFFSET 0x60
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define TCO1_CNT 0x08
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#define TCO_TMR_HLT (1 << 11)
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#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */
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@ -27,11 +27,11 @@ void watchdog_off(void)
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/* Disable the watchdog timer. */
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value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
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value |= TCO_TMR_HLT;
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value |= TCO1_TMR_HLT;
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write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
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/* Clear TCO timeout status. */
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write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT);
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write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_STS_TIMEOUT);
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write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
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printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
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