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soc/intel/apollolake: Add Page table mapping for System Memory 

Since we do not know before hand the memory range initialized by FSP memory
init until it completes and as memory gets accessed from within FSP memory
init to migrate FSP from CAR to memory, we need to add this mapping in
coreboot.

Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Hannah Williams 2018-05-31 19:16:09 -07:00 committed by Martin Roth
parent 22e6018b28
commit 067d38a7af
3 changed files with 1670 additions and 47 deletions
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6
src/soc/intel/apollolake/glk_page_map.txt
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@ -1,3 +1,9 @@
0x00000000, 0x100000000, WB, # RAM
# Above entry is needed because below 4G allocated memory range is
# only known after FSP memory init completes. However, FSP migrates to memory
# from cache as ram before it exits FSP Memory Init. Hence we need to add
# page table entries for this entire range before FSP Memory Init. The
# overlapped MMIO ranges will be overridden by below entries.
0xd0000000, 0x100000000, UC, NX # All of MMIO 0xd0000000, 0x100000000, UC, NX # All of MMIO
# Maximum 16MiB of mmio SPI flash decode. # Maximum 16MiB of mmio SPI flash decode.
0xff000000, 0x100000000, WP, # memory-mapped SPI 0xff000000, 0x100000000, WP, # memory-mapped SPI

1668
src/soc/intel/apollolake/pt.c
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File diff suppressed because it is too large Load Diff

43
src/soc/intel/apollolake/romstage.c
View File

@ -248,13 +248,6 @@ asmlinkage void car_stage_entry(void)
tseg_base = (uintptr_t)smm_base; tseg_base = (uintptr_t)smm_base;
postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
/* Ensure TSEG has mappings. */
if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) {
if (paging_identity_map_addr(tseg_base, smm_size, PAT_WB))
printk(BIOS_ERR, "Unable to map TSEG: %lx--%lx\n",
tseg_base, tseg_base + smm_size);
}
run_postcar_phase(&pcf); run_postcar_phase(&pcf);
} }
@ -343,40 +336,6 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd)
#endif #endif
} }
static void prepare_fspm_pages(void)
{
const size_t mib128 = 128 * MiB;
uintptr_t base;
/* All in units of MiB */
size_t mem_sz;
size_t iohole_sz;
size_t low_mem_sz;
mem_sz = memory_in_system_in_mib();
if (!mem_sz) {
printk(BIOS_ERR, "No memory in system! FSP will hang...\n");
return;
}
iohole_sz = iohole_in_mib();
/* Mark pages as WB where FSP will write. One region will be in cbmem,
but it's not clear what else FSP is writing to. Try to make the best
calculation. */
low_mem_sz = 4 * (GiB / MiB) - iohole_sz;
if (low_mem_sz > mem_sz)
low_mem_sz = mem_sz;
/* Assume all accesses are within 128MiB of the crude low memory
calculation above. */
base = low_mem_sz * MiB - mib128;
if (paging_identity_map_addr(base, mib128, PAT_WB))
printk(BIOS_ERR, "Unable to map %lx--%lx\n", base,
base + mib128);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{ {
struct region_device rdev; struct region_device rdev;
@ -430,8 +389,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
car_set_var(fsp_version, version); car_set_var(fsp_version, version);
if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM))
prepare_fspm_pages();
} }
__weak __weak