kunimitsu: Add initial FSP2.0 support

Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.

Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Rizwan Qureshi 2016-08-23 13:38:19 +05:30 committed by Martin Roth
parent d2ec56985f
commit 06868f8154
4 changed files with 27 additions and 2 deletions

View File

@ -34,3 +34,7 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
endif

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@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */

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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/romstage.h>
void mainboard_memory_init_params(struct FSPM_UPD *mupd)
{
/* TODO: Read and copy SPD and fill up Rcomp and DQ param */
}

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@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
romstage-y += spd.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin