kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact. Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -34,3 +34,7 @@ ramstage-y += pei_data.c
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ramstage-y += ramstage.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
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romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
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endif
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@ -16,7 +16,7 @@
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#include <soc/ramstage.h>
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#include "gpio.h"
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void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
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void mainboard_silicon_init_params(FSP_SIL_UPD *params)
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{
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/* Configure pads prior to SiliconInit() in case there's any
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* dependencies during hardware initialization. */
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/romstage.h>
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void mainboard_memory_init_params(struct FSPM_UPD *mupd)
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{
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/* TODO: Read and copy SPD and fill up Rcomp and DQ param */
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}
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@ -14,7 +14,7 @@
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## GNU General Public License for more details.
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##
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romstage-y += spd.c
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
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SPD_BIN = $(obj)/spd.bin
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