google/kukui: Support TPM

Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ,
implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM
interrupt.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.

Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/mainboard/google/kukui/Kconfig

@@ -2,7 +2,6 @@ if BOARD_GOOGLE_KUKUI
 
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select VBOOT_MOCK_SECDATA
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -15,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_SPI
+	select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT
 
 config MAINBOARD_DIR
 	string
@@ -24,6 +25,10 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Kukui"
 
+config DRIVER_TPM_SPI_BUS
+	hex
+	default 0x0
+
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 1

src/mainboard/google/kukui/Makefile.inc

@@ -5,6 +5,7 @@ bootblock-y += memlayout.ld
 decompressor-y += memlayout.ld
 
 verstage-y += chromeos.c
+verstage-y += verstage.c
 verstage-y += memlayout.ld
 
 romstage-y += boardid.c

src/mainboard/google/kukui/chromeos.c

@@ -16,6 +16,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <security/tpm/tis.h>
 
 #include "gpio.h"
 
@@ -31,6 +32,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
 		{EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"},
 		{EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"},
+		{CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
@@ -39,3 +41,8 @@ int get_write_protect_state(void)
 {
 	return 0;
 }
+
+int tis_plat_irq_status(void)
+{
+	return gpio_eint_poll(CR50_IRQ);
+}

src/mainboard/google/kukui/gpio.h

@@ -20,6 +20,7 @@
 
 #define EC_IRQ		GPIO(PERIPHERAL_EN1)
 #define EC_IN_RW	GPIO(PERIPHERAL_EN14)
+#define CR50_IRQ	GPIO(PERIPHERAL_EN3)
 
 void setup_chromeos_gpios(void);
 

src/mainboard/google/kukui/verstage.c

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <security/vboot/vboot_common.h>
+#include <soc/gpio.h>
+#include <soc/spi.h>
+
+#include "gpio.h"
+
+void verstage_mainboard_init(void)
+{
+	mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz);
+	gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
+}