src/include/console: Get rid of unused deprecated POST codes
Change-Id: Id577b7c1421e9ffc3f51e90fcc9330c8f3be9a56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Elyes HAOUAS
Patrick Georgi
parent
81e3b74301
commit
0688bce81c
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@ -417,177 +417,4 @@
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*/
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#define POST_DIE 0xff
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/*
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* The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
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* They overlap with previous codes, and most are not even used
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* Some mainboards still require them, but they are deprecated. We want to
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* consolidate our own POST code structure with the codes above.
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*
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* standard AMD post definitions for the AMD Geode
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*/
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/* port to write post codes to */
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#define POST_Output_Port (0x080)
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#define POST_preSioInit (0x000)
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#define POST_clockInit (0x001)
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#define POST_CPURegInit (0x002)
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#define POST_UNREAL (0x003)
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#define POST_CPUMemRegInit (0x004)
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#define POST_CPUTest (0x005)
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#define POST_memSetup (0x006)
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#define POST_memSetUpStack (0x007)
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#define POST_memTest (0x008)
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#define POST_shadowRom (0x009)
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#define POST_memRAMoptimize (0x00A)
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#define POST_cacheInit (0x00B)
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#define POST_northBridgeInit (0x00C)
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#define POST_chipsetInit (0x00D)
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#define POST_sioTest (0x00E)
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#define POST_pcATjunk (0x00F)
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#define POST_intTable (0x010)
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#define POST_memInfo (0x011)
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#define POST_romCopy (0x012)
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#define POST_PLLCheck (0x013)
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#define POST_keyboardInit (0x014)
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#define POST_cpuCacheOff (0x015)
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#define POST_BDAInit (0x016)
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#define POST_pciScan (0x017)
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#define POST_optionRomInit (0x018)
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#define POST_ResetLimits (0x019)
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#define POST_summary_screen (0x01A)
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#define POST_Boot (0x01B)
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#define POST_SystemPreInit (0x01C)
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#define POST_ClearRebootFlag (0x01D)
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#define POST_GLIUInit (0x01E)
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#define POST_BootFailed (0x01F)
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#define POST_CPU_ID (0x020)
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#define POST_COUNTERBROKEN (0x021)
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#define POST_DIFF_DIMMS (0x022)
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#define POST_WIGGLE_MEM_LINES (0x023)
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#define POST_NO_GLIU_DESC (0x024)
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#define POST_CPU_LCD_CHECK (0x025)
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#define POST_CPU_LCD_PASS (0x026)
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#define POST_CPU_LCD_FAIL (0x027)
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#define POST_CPU_STEPPING (0x028)
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#define POST_CPU_DM_BIST_FAILURE (0x029)
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#define POST_CPU_FLAGS (0x02A)
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#define POST_CHIPSET_ID (0x02B)
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#define POST_CHIPSET_ID_PASS (0x02C)
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#define POST_CHIPSET_ID_FAIL (0x02D)
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#define POST_CPU_ID_GOOD (0x02E)
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#define POST_CPU_ID_FAIL (0x02F)
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/* PCI config*/
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#define P80_PCICFG (0x030)
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/* PCI io*/
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#define P80_PCIIO (0x040)
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/* PCI memory*/
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#define P80_PCIMEM (0x050)
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/* SIO*/
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#define P80_SIO (0x060)
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/* Memory Setp*/
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#define P80_MEM_SETUP (0x070)
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#define POST_MEM_SETUP (0x070)
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#define ERROR_32BIT_DIMMS (0x071)
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#define POST_MEM_SETUP2 (0x072)
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#define POST_MEM_SETUP3 (0x073)
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#define POST_MEM_SETUP4 (0x074)
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#define POST_MEM_SETUP5 (0x075)
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#define POST_MEM_ENABLE (0x076)
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#define ERROR_NO_DIMMS (0x077)
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#define ERROR_DIFF_DIMMS (0x078)
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#define ERROR_BAD_LATENCY (0x079)
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#define ERROR_SET_PAGE (0x07A)
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#define ERROR_DENSITY_DIMM (0x07B)
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#define ERROR_UNSUPPORTED_DIMM (0x07C)
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#define ERROR_BANK_SET (0x07D)
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#define POST_MEM_SETUP_GOOD (0x07E)
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#define POST_MEM_SETUP_FAIL (0x07F)
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#define POST_UserPreInit (0x080)
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#define POST_UserPostInit (0x081)
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#define POST_Equipment_check (0x082)
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#define POST_InitNVRAMBX (0x083)
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#define POST_NoPIRTable (0x084)
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#define POST_ChipsetFingerPrintPass (0x085)
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#define POST_ChipsetFingerPrintFail (0x086)
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#define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
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#define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
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#define POST_CPU_FPU_BIST_FAILURE (0x089)
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#define POST_CPU_BTB_BIST_FAILURE (0x08A)
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#define POST_CPU_EX_BIST_FAILURE (0x08B)
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#define POST_Chipset_PI_Test_Fail (0x08C)
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D)
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#define POST_BIT_CLK_Fail (0x08E)
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#define POST_STACK_SETUP (0x090)
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#define POST_CPU_PF_BIST_FAILURE (0x091)
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#define POST_CPU_L2_BIST_FAILURE (0x092)
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#define POST_CPU_GLCP_BIST_FAILURE (0x093)
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#define POST_CPU_DF_BIST_FAILURE (0x094)
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#define POST_CPU_VG_BIST_FAILURE (0x095)
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#define POST_CPU_VIP_BIST_FAILURE (0x096)
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#define POST_STACK_SETUP_PASS (0x09E)
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#define POST_STACK_SETUP_FAIL (0x09F)
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#define POST_PLL_INIT (0x0A0)
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#define POST_PLL_MANUAL (0x0A1)
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#define POST_PLL_STRAP (0x0A2)
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#define POST_PLL_RESET_FAIL (0x0A3)
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#define POST_PLL_PCI_FAIL (0x0A4)
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#define POST_PLL_MEM_FAIL (0x0A5)
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#define POST_PLL_CPU_VER_FAIL (0x0A6)
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#define POST_MEM_TESTMEM (0x0B0)
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#define POST_MEM_TESTMEM1 (0x0B1)
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#define POST_MEM_TESTMEM2 (0x0B2)
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#define POST_MEM_TESTMEM3 (0x0B3)
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#define POST_MEM_TESTMEM4 (0x0B4)
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#define POST_MEM_TESTMEM_PASS (0x0BE)
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#define POST_MEM_TESTMEM_FAIL (0x0BF)
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#define POST_SECUROM_SECBOOT_START (0x0C0)
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#define POST_SECUROM_BOOTSRCSETUP (0x0C1)
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#define POST_SECUROM_REMAP_FAIL (0x0C2)
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#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
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#define POST_SECUROM_DCACHESETUP (0x0C4)
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#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5)
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#define POST_SECUROM_ICACHESETUP (0x0C6)
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#define POST_SECUROM_DESCRIPTORSETUP (0x0C7)
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#define POST_SECUROM_DCACHESETUPBIOS (0x0C8)
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#define POST_SECUROM_PLATFORMSETUP (0x0C9)
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#define POST_SECUROM_SIGCHECKBIOS (0x0CA)
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#define POST_SECUROM_ICACHESETUPBIOS (0x0CB)
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#define POST_SECUROM_PASS (0x0CC)
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#define POST_SECUROM_FAIL (0x0CD)
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#define POST_RCONFInitError (0x0CE)
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#define POST_CacheInitError (0x0CF)
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#define POST_ROM_PREUNCOMPRESS (0x0D0)
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#define POST_ROM_UNCOMPRESS (0x0D1)
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#define POST_ROM_SMM_INIT (0x0D2)
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#define POST_ROM_VID_BIOS (0x0D3)
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#define POST_ROM_LCDINIT (0x0D4)
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#define POST_ROM_SPLASH (0x0D5)
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#define POST_ROM_HDDINIT (0x0D6)
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#define POST_ROM_SYS_INIT (0x0D7)
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#define POST_ROM_DMM_INIT (0x0D8)
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#define POST_ROM_TVINIT (0x0D9)
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#define POST_ROM_POSTUNCOMPRESS (0x0DE)
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#define P80_CHIPSET_INIT (0x0E0)
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#define POST_PreChipsetInit (0x0E1)
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#define POST_LateChipsetInit (0x0E2)
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#define POST_NORTHB_INIT (0x0E8)
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#define POST_INTR_SEG_JUMP (0x0F0)
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#endif /* POST_CODES_H */
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