northbridge/amd/amdmct: Allow override of memory settings via NVRAM
This patch allows the following memory controller settings to be overridden in NVRAM: Memory frequency limit ECC enable ECC scrub rate Change-Id: Ibfde3d888b0f81a29a14af2d142171510b87655e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8438 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -20,9 +20,23 @@
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/* Call-backs */
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/* Call-backs */
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#include <delay.h>
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#include <delay.h>
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#define NVRAM_DDR2_800 0
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#define NVRAM_DDR2_667 1
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#define NVRAM_DDR2_533 2
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#define NVRAM_DDR2_400 3
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#define NVRAM_DDR3_1600 0
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#define NVRAM_DDR3_1333 1
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#define NVRAM_DDR3_1066 2
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#define NVRAM_DDR3_800 3
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static const uint16_t ddr2_limits[4] = {400, 333, 266, 200};
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static const uint16_t ddr3_limits[4] = {800, 666, 533, 400};
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static u16 mctGet_NVbits(u8 index)
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static u16 mctGet_NVbits(u8 index)
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{
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{
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u16 val = 0;
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u16 val = 0;
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int nvram;
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switch (index) {
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switch (index) {
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case NV_PACK_TYPE:
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case NV_PACK_TYPE:
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@ -45,10 +59,16 @@ static u16 mctGet_NVbits(u8 index)
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break;
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break;
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case NV_MAX_MEMCLK:
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case NV_MAX_MEMCLK:
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/* Maximum platform supported memclk */
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/* Maximum platform supported memclk */
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//val = 200; /* 200MHz(DDR400) */
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val = MEM_MAX_LOAD_FREQ;
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//val = 266; /* 266MHz(DDR533) */
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//val = 333; /* 333MHz(DDR667) */
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if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) {
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val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */
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int limit = val;
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if (IS_ENABLED(CONFIG_DIMM_DDR3))
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limit = ddr3_limits[nvram & 3];
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else if (IS_ENABLED(CONFIG_DIMM_DDR2))
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limit = ddr2_limits[nvram & 3];
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val = min(limit, val);
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}
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break;
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break;
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case NV_ECC_CAP:
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case NV_ECC_CAP:
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#if SYSTEM_TYPE == SERVER
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#if SYSTEM_TYPE == SERVER
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@ -91,6 +111,9 @@ static u16 mctGet_NVbits(u8 index)
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/* Bank (chip select) interleaving */
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/* Bank (chip select) interleaving */
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//val = 0; /* disabled */
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//val = 0; /* disabled */
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val = 1; /* enabled (recommended) */
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val = 1; /* enabled (recommended) */
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if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS)
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val = !!nvram;
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break;
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break;
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case NV_MemHole:
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case NV_MemHole:
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//val = 0; /* Disabled */
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//val = 0; /* Disabled */
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@ -111,6 +134,9 @@ static u16 mctGet_NVbits(u8 index)
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case NV_NodeIntlv:
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case NV_NodeIntlv:
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val = 0; /* Disabled (recommended) */
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val = 0; /* Disabled (recommended) */
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//val = 1; /* Enable */
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//val = 1; /* Enable */
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if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS)
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val = !!nvram;
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break;
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break;
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case NV_BurstLen32:
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case NV_BurstLen32:
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#if !CONFIG_GFXUMA
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#if !CONFIG_GFXUMA
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@ -151,6 +177,9 @@ static u16 mctGet_NVbits(u8 index)
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#else
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#else
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val = 0; /* Disable */
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val = 0; /* Disable */
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#endif
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#endif
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if (get_option(&nvram, "ECC_memory") == CB_SUCCESS)
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val = !!nvram;
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break;
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break;
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case NV_NBECC:
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case NV_NBECC:
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#if (SYSTEM_TYPE == SERVER)
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#if (SYSTEM_TYPE == SERVER)
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@ -172,6 +201,9 @@ static u16 mctGet_NVbits(u8 index)
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* 1: Enable
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* 1: Enable
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*/
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*/
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val = CONFIG_AMDMCT_ENABLE_ECC_REDIR;
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val = CONFIG_AMDMCT_ENABLE_ECC_REDIR;
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if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS)
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val = !!nvram;
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break;
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break;
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case NV_DramBKScrub:
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case NV_DramBKScrub:
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/*
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/*
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@ -200,6 +232,9 @@ static u16 mctGet_NVbits(u8 index)
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* 0x16: 84ms
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* 0x16: 84ms
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*/
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*/
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val = CONFIG_AMDMCT_BACKGROUND_SCRUB_RATE;
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val = CONFIG_AMDMCT_BACKGROUND_SCRUB_RATE;
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if ((get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) && (nvram <= 0x16))
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val = nvram;
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break;
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break;
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case NV_L2BKScrub:
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case NV_L2BKScrub:
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val = 0; /* Disabled - See L2Scrub in BKDG */
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val = 0; /* Disabled - See L2Scrub in BKDG */
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@ -219,6 +254,9 @@ static u16 mctGet_NVbits(u8 index)
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/* channel interleave is better performance than ganged mode at this time */
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/* channel interleave is better performance than ganged mode at this time */
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val = 1; /* Enabled */
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val = 1; /* Enabled */
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//val = 0; /* Disabled */
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//val = 0; /* Disabled */
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if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS)
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val = !!nvram;
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break;
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break;
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case NV_ChannelIntlv:
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case NV_ChannelIntlv:
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val = 5; /* Not currently checked in mctchi_d.c */
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val = 5; /* Not currently checked in mctchi_d.c */
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