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nb/intel/sandybridge/raminit: Define registers 

Use register names found on forums.corsair.com.
No functionality changed.

Change-Id: Ibaede39a24e8df1c4d42cb27986ab66174b7d45b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17400
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Patrick Rudolph 2016-11-12 11:43:59 +01:00
parent f704754847
commit 069018d69a
1 changed files with 8 additions and 5 deletions
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13
src/northbridge/intel/sandybridge/raminit.c
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@ -203,6 +203,9 @@ typedef struct ramctr_timing_st {
#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)
#define GET_ERR_CHANNEL(x) (x>>16) #define GET_ERR_CHANNEL(x) (x>>16)
#define MC_BIOS_REQ 0x5e00
#define MC_BIOS_DATA 0x5e04
static void program_timings(ramctr_timing * ctrl, int channel); static void program_timings(ramctr_timing * ctrl, int channel);
static unsigned int get_mmio_size(void); static unsigned int get_mmio_size(void);
@ -311,7 +314,7 @@ static void report_memory_config(void)
addr_decode_ch[1] = MCHBAR32(0x5008); addr_decode_ch[1] = MCHBAR32(0x5008);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100); (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 4) & 3); (addr_decoder_common >> 4) & 3);
@ -832,7 +835,7 @@ static void dram_freq(ramctr_timing * ctrl)
/* The PLL will never lock if the required frequency is /* The PLL will never lock if the required frequency is
* already set. Exit early to prevent a system hang. * already set. Exit early to prevent a system hang.
*/ */
reg1 = MCHBAR32(0x5e04); reg1 = MCHBAR32(MC_BIOS_DATA);
val2 = (u8) reg1; val2 = (u8) reg1;
if (val2) if (val2)
return; return;
@ -840,15 +843,15 @@ static void dram_freq(ramctr_timing * ctrl)
/* Step 2 - Select frequency in the MCU */ /* Step 2 - Select frequency in the MCU */
reg1 = FRQ; reg1 = FRQ;
reg1 |= 0x80000000; // set running bit reg1 |= 0x80000000; // set running bit
MCHBAR32(0x5e00) = reg1; MCHBAR32(MC_BIOS_REQ) = reg1;
while (reg1 & 0x80000000) { while (reg1 & 0x80000000) {
printk(BIOS_DEBUG, " PLL busy..."); printk(BIOS_DEBUG, " PLL busy...");
reg1 = MCHBAR32(0x5e00); reg1 = MCHBAR32(MC_BIOS_REQ);
} }
printk(BIOS_DEBUG, "done\n"); printk(BIOS_DEBUG, "done\n");
/* Step 3 - Verify lock frequency */ /* Step 3 - Verify lock frequency */
reg1 = MCHBAR32(0x5e04); reg1 = MCHBAR32(MC_BIOS_DATA);
val2 = (u8) reg1; val2 = (u8) reg1;
if (val2 >= FRQ) { if (val2 >= FRQ) {
printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n",