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google/chell: Enable eMMC HS400 mode 

Hynix eMMC can now run under HS400 mode.

BUG=chrome-os-partner:47647
TEST=run consective boot 100 times on Chell EVT Hynix SKU, and
MMC errors didn't happen.
BRANCH=none

Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca
Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319627
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ryan Lin 2015-12-25 10:54:44 +08:00 committed by Patrick Georgi
parent bc58a878cd
commit 0691f25e53
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/chell/devicetree.cb
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@ -35,7 +35,7 @@ chip soc/intel/skylake
register "SmbusEnable" = "1" register "SmbusEnable" = "1"
register "Cio2Enable" = "0" register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1" register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0" register "ScsSdCardEnabled" = "0"
register "IshEnable" = "0" register "IshEnable" = "0"
register "PttSwitch" = "0" register "PttSwitch" = "0"