mainboard: Drop print_ implementation from non-romcc boards

Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the mainboard code to use printk() on all non-ROMCC
boards.

Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8111
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

src/mainboard/advansus/a785e-i/romstage.c

@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/amd/bimini_fam10/romstage.c

@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/amd/dbm690t/romstage.c

@@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/amd/dinar/romstage.c

@@ -98,9 +98,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 
 	post_code(0x43);
-	print_debug("Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as ram ");
 	disable_cache_as_ram();
-	print_debug("done\n");
+	printk(BIOS_DEBUG, "done\n");
 
 	post_code(0x44);
 	copy_and_run();

src/mainboard/amd/mahogany/romstage.c

@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/amd/pistachio/romstage.c

@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x06);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/amd/rumba/romstage.c

@@ -50,7 +50,7 @@ void main(unsigned long bist)
 	pll_reset();
 
 	cpuRegInit();
-	print_err("done cpuRegInit\n");
+	printk(BIOS_ERR, "done cpuRegInit\n");
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_pci_device(PCI_DEV(0, 0x19, 0));
 #endif
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 	setup_coherent_ht_domain(); // routing table and start other core0
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* Read FIDVID_STATUS */
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
 	enable_fid_change();
@@ -160,11 +160,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
 	} else {
-		print_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 #endif
 
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 #endif

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -283,7 +283,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}
@@ -292,7 +292,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* FIXME:  Move this to chipset init.
 	enable cf9 for hard reset */
-	print_debug("enable_cf9_x()\n");
+	printk(BIOS_DEBUG, "enable_cf9_x()\n");
 	enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
 	post_code(0x3C);
 

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/arima/hdama/debug.c

@@ -1,77 +0,0 @@
-
-static void dump_spd_registers(int controllers, const struct mem_controller *ctrl)
-{
-	int n;
-	for(n = 0; n < controllers; n++) {
-		int i;
-		print_debug("\n");
-		activate_spd_rom(&ctrl[n]);
-		for(i = 0; i < 4; i++) {
-			unsigned device;
-			device = ctrl[n].channel0[i];
-			if (device) {
-				int j;
-				print_debug("dimm: ");
-				print_debug_hex8(n);
-				print_debug_char('.');
-				print_debug_hex8(i);
-				print_debug(".0: ");
-				print_debug_hex8(device);
-				for(j = 0; j < 256; j++) {
-					int status;
-					unsigned char byte;
-					if ((j & 0xf) == 0) {
-						print_debug("\n");
-						print_debug_hex8(j);
-						print_debug(": ");
-					}
-					status = spd_read_byte(device, j);
-					if (status < 0) {
-						print_debug("bad device\n");
-						break;
-					}
-#if 0
-					byte = status & 0xff;
-					print_debug_hex8(byte);
-#else
-					print_debug_hex8(status & 0xff);
-#endif
-					print_debug_char(' ');
-				}
-				print_debug("\n");
-			}
-			device = ctrl[n].channel1[i];
-			if (device) {
-				int j;
-				print_debug("dimm: ");
-				print_debug_hex8(n);
-				print_debug_char('.');
-				print_debug_hex8(i);
-				print_debug(".1: ");
-				print_debug_hex8(device);
-				for(j = 0; j < 256; j++) {
-					int status;
-					unsigned char byte;
-					if ((j & 0xf) == 0) {
-						print_debug("\n");
-						print_debug_hex8(j);
-						print_debug(": ");
-					}
-					status = spd_read_byte(device, j);
-					if (status < 0) {
-						print_debug("bad device\n");
-						break;
-					}
-#if 0
-					byte = status & 0xff;
-					print_debug_hex8(byte);
-#else
-					print_debug_hex8(status & 0xff);
-#endif
-					print_debug_char(' ');
-				}
-				print_debug("\n");
-			}
-		}
-	}
-}

src/mainboard/arima/hdama/romstage.c

@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-	       	print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 	       	soft_reset();
        	}
 

src/mainboard/artecgroup/dbe61/romstage.c

@@ -95,31 +95,12 @@ void main(unsigned long bist)
 	/* Dump memory configuration. */
 #if 0
 	msr = rdmsr(MC_CF07_DATA);
-	print_debug("MC_CF07_DATA: ");
+	printk(BIOS_DEBUG, "MC_CF07_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
-	print_debug_hex32(MC_CF07_DATA);
-	print_debug(" value is: ");
-	print_debug_hex32(msr.hi);
-	print_debug(":");
-	print_debug_hex32(msr.lo);
-	print_debug("\n");
 
 	msr = rdmsr(MC_CF1017_DATA);
-	print_debug("MC_CF1017_DATA: ");
+	printk(BIOS_DEBUG, "MC_CF1017_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
-	print_debug_hex32(MC_CF1017_DATA);
-	print_debug(" value is: ");
-	print_debug_hex32(msr.hi);
-	print_debug(":");
-	print_debug_hex32(msr.lo);
-	print_debug("\n");
 
 	msr = rdmsr(MC_CF8F_DATA);
-	print_debug("MC_CF8F_DATA: ");
+	printk(BIOS_DEBUG, "MC_CF8F_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
-	print_debug_hex32(MC_CF8F_DATA);
-	print_debug(" value is: ");
-	print_debug_hex32(msr.hi);
-	print_debug(":");
-	print_debug_hex32(msr.lo);
-	msr = rdmsr(MC_CF8F_DATA);
-	print_debug("\n");
 #endif
 }

src/mainboard/asrock/939a785gmh/romstage.c

@@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/asus/a8n_e/romstage.c

@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= ht_setup_chains_x();
 	needs_reset |= ck804_early_setup_x();
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -65,7 +65,7 @@ void soft_reset(void)
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset\n");
+	printk(BIOS_DEBUG, "soft reset\n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... romstage\n");
+	printk(BIOS_INFO, "now booting... romstage\n");
 
 	/* Is this a CPU only reset? Or is this a secondary CPU? */
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 	}
 
-	print_info("now booting... real_main\n");
+	printk(BIOS_INFO, "now booting... real_main\n");
 
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
 
-	print_info("now booting... Core0 started\n");
+	printk(BIOS_INFO, "now booting... Core0 started\n");
 
 #if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= k8t890_early_setup_ht();
 
 	if (needs_reset) {
-		print_debug("ht reset -\n");
+		printk(BIOS_DEBUG, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/asus/a8v-e_se/romstage.c

@@ -65,7 +65,7 @@ void soft_reset(void)
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset\n");
+	printk(BIOS_DEBUG, "soft reset\n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... fallback\n");
+	printk(BIOS_INFO, "now booting... fallback\n");
 
 	/* Is this a CPU only reset? Or is this a secondary CPU? */
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 	}
 
-	print_info("now booting... real_main\n");
+	printk(BIOS_INFO, "now booting... real_main\n");
 
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
 
-	print_info("now booting... Core0 started\n");
+	printk(BIOS_INFO, "now booting... Core0 started\n");
 
 #if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= k8t890_early_setup_ht();
 
 	if (needs_reset) {
-		print_debug("ht reset -\n");
+		printk(BIOS_DEBUG, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/asus/k8v-x/romstage.c

@@ -63,7 +63,7 @@ void soft_reset(void)
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset\n");
+	printk(BIOS_DEBUG, "soft reset\n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... fallback\n");
+	printk(BIOS_INFO, "now booting... fallback\n");
 
 	/* Is this a CPU only reset? Or is this a secondary CPU? */
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 	}
 
-	print_info("now booting... real_main\n");
+	printk(BIOS_INFO, "now booting... real_main\n");
 
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
 
-	print_info("now booting... Core0 started\n");
+	printk(BIOS_INFO, "now booting... Core0 started\n");
 
 #if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= k8t890_early_setup_ht();
 
 	if (needs_reset) {
-		print_debug("ht reset -\n");
+		printk(BIOS_DEBUG, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/asus/m2n-e/romstage.c

@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * effective too.
 	 */
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 	allow_all_aps_stop(bsp_apicid);

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -70,7 +70,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void ldtstop_sb(void)
 {
-	print_debug("toggle LDTSTP#\n");
+	printk(BIOS_DEBUG, "toggle LDTSTP#\n");
 
 	/* fix errata #181, disable DRAM controller it will get enabled later */
 	u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
@@ -81,7 +81,7 @@ static void ldtstop_sb(void)
 	reg = reg ^ (1 << 0);
 	outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
 	reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
-	print_debug("done\n");
+	printk(BIOS_DEBUG, "done\n");
 }
 
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -92,7 +92,7 @@ void soft_reset(void)
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset\n");
+	printk(BIOS_DEBUG, "soft reset\n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -154,11 +154,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
 	needs_reset = optimize_link_coherent_ht();
-	print_debug_hex8(needs_reset);
+	printk(BIOS_DEBUG, "%02x", needs_reset);
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-	print_debug_hex8(needs_reset);
+	printk(BIOS_DEBUG, "%02x", needs_reset);
 	needs_reset |= k8t890_early_setup_ht();
-	print_debug_hex8(needs_reset);
+	printk(BIOS_DEBUG, "%02x", needs_reset);
 
 	vt8237_early_network_init(NULL);
 	vt8237_early_spi_init();
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	vt8237_sb_enable_fid_vid();
 
 	enable_fid_change();
-	print_debug("after enable_fid_change\n");
+	printk(BIOS_DEBUG, "after enable_fid_change\n");
 
 	init_fidvid_bsp(bsp_apicid);
 

src/mainboard/asus/m2v/romstage.c

@@ -76,7 +76,7 @@ void soft_reset(void)
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset\n");
+	printk(BIOS_DEBUG, "soft reset\n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -254,11 +254,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
 	needs_reset = optimize_link_coherent_ht();
-	print_debug_hex8(needs_reset);
+	printk(BIOS_DEBUG, "%02x", needs_reset);
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-	print_debug_hex8(needs_reset);
+	printk(BIOS_DEBUG, "%02x", needs_reset);
 	needs_reset |= k8t890_early_setup_ht();
-	print_debug_hex8(needs_reset);
+	printk(BIOS_DEBUG, "%02x", needs_reset);
 
 	if (needs_reset) {
 		printk(BIOS_DEBUG, "ht reset -\n");
@@ -271,7 +271,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	vt8237_sb_enable_fid_vid();
 
 	enable_fid_change();
-	print_debug("after enable_fid_change\n");
+	printk(BIOS_DEBUG, "after enable_fid_change\n");
 
 	init_fidvid_bsp(bsp_apicid);
 

src/mainboard/asus/m4a78-em/romstage.c

@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/asus/m4a785-m/romstage.c

@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/asus/m5a88-v/romstage.c

@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/avalue/eax-785e/romstage.c

@@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/broadcom/blast/romstage.c

@@ -79,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
         setup_blast_resource_map();
 
@@ -101,10 +101,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	bcm5785_early_setup();
 
-       	if (needs_reset) {
+	if (needs_reset) {
-               	print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
-               	soft_reset();
+		soft_reset();
-       	}
+	}
 
 	allow_all_aps_stop(bsp_apicid);
 

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -73,7 +73,7 @@ void main(unsigned long bist)
 	*/
 	post_code(0x02);
 	__asm__("wbinvd\n");
-	print_err("Past wbinvd\n");
+	printk(BIOS_ERR, "Past wbinvd\n");
 	/* we are finding the return does not work on this board. Explicitly call the label that is
 	 * after the call to us. This is gross, but sometimes at this level it is the only way out
 	 */

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+        printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
         setup_coherent_ht_domain(); // routing table and start other core0
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
         enable_fid_change();
         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
 
@@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
               	soft_reset();
         }
         allow_all_aps_stop(bsp_apicid);

src/mainboard/gigabyte/m57sli/romstage.c

@@ -144,9 +144,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1);
-
+        printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
         setup_coherent_ht_domain(); // routing table and start other core0
@@ -169,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
         enable_fid_change();
         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -178,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
 
@@ -190,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
               	soft_reset();
         }
         allow_all_aps_stop(bsp_apicid);

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/hp/dl145_g1/romstage.c

@@ -64,14 +64,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
 static inline void change_i2c_mux(unsigned device)
 {
 	int ret, i;
-	print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
+	printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
 	i=2;
 	do {
 		ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-		print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
+		printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
 	} while ((ret!=0) && (i-->0));
 	ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
-	print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
+	printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
 }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* Read FIDVID_STATUS */
 			msr_t msr;
 			msr=rdmsr(0xc0010042);
-			print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+			printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 		}
 
 		enable_fid_change();
@@ -154,11 +154,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		{
 			msr_t msr;
 			msr=rdmsr(0xc0010042);
-			print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+			printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 		}
 
 	} else {
-		print_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 #endif
 
@@ -166,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 	}
 

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/ibm/e325/romstage.c

@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/ibm/e326/romstage.c

@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/intel/eagleheights/debug.c

@@ -28,11 +28,7 @@ static void print_reg(unsigned char index)
 
         outb(index, 0x2e);
         data = inb(0x2f);
-	print_debug("0x");
+	printk(BIOS_DEBUG, "0x%02x: 0x%02x\n", index, data);
-	print_debug_hex8(index);
-	print_debug(": 0x");
-	print_debug_hex8(data);
-	print_debug("\n");
         return;
 }
 
@@ -69,52 +65,49 @@ static inline void siodump(void)
         int i;
         unsigned char data;
 
-	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
+	 printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0
-        print_debug("\n*** XBUS REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
 
-        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
 
-        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\n***  GPIO REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\n***  GPIO VALUES ***\n");
+        printk(BIOS_DEBUG, "\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\nGPDO 4: 0x");
+	printk(BIOS_DEBUG, "\nGPDO 4: 0x%02x", data);
-	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\nGPDI 4: 0x");
+	printk(BIOS_DEBUG, "\nGPDI 4: 0x%02x\n", data);
-	print_debug_hex8(data);
-	print_debug("\n");
 
 #if 0
 
-        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
 
-        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\n***  RTC REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -124,7 +117,7 @@ static inline void siodump(void)
         print_reg(0xfe);
         print_reg(0xff);
 
-        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
+        printk(BIOS_DEBUG, "\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif
@@ -136,27 +129,21 @@ static inline void dump_bar14(unsigned dev)
 	int i;
 	unsigned long bar;
 
-	print_debug("BAR 14 Dump\n");
+	printk(BIOS_DEBUG, "BAR 14 Dump\n");
 
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
 #if 0
 		unsigned char val;
-		if ((i & 0x0f) == 0) {
+		if ((i & 0x0f) == 0)
-			print_debug_hex8(i);
+			printk(BIOS_DEBUG, "%02x:", i);
-			print_debug_char(':');
-		}
 		val = pci_read_config8(dev, i);
 #endif
-		if((i%4)==0) {
+		if((i%4)==0)
-		print_debug("\n");
+			printk(BIOS_DEBUG, "\n%04x ", i);
-		print_debug_hex16(i);
+		printk(BIOS_DEBUG, "%08x ", read32(bar + i));
-		print_debug_char(' ');
-		}
-		print_debug_hex32(read32(bar + i));
-		print_debug_char(' ');
 	}
-	print_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static inline void dump_spd_registers(void)
@@ -166,28 +153,20 @@ static inline void dump_spd_registers(void)
         while(device <= DIMM7) {
                 int status = 0;
                 int i;
-        	print_debug("\n");
+                printk(BIOS_DEBUG, "\ndimm %02x", device);
-                print_debug("dimm ");
-		print_debug_hex8(device);
 
                 for(i = 0; (i < 256) ; i++) {
-                        if ((i % 16) == 0) {
+                        if ((i % 16) == 0)
-				print_debug("\n");
+				printk(BIOS_DEBUG, "\n%02x: ", i);
-				print_debug_hex8(i);
-				print_debug(": ");
-                        }
 			status = smbus_read_byte(device, i);
                         if (status < 0) {
-			         print_debug("bad device: ");
+			         printk(BIOS_DEBUG, "bad device: %d\n", -status);
-				 print_debug_hex8(-status);
-				 print_debug("\n");
 			         break;
 			}
-			print_debug_hex8(status);
+			printk(BIOS_DEBUG, "%02x ", status);
-			print_debug_char(' ');
 		}
 		device++;
-		print_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 
@@ -198,22 +177,17 @@ static inline void dump_ipmi_registers(void)
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\n");
+                printk(BIOS_DEBUG, "\nipmi %02x", device);
-                print_debug("ipmi ");
-		print_debug_hex8(device);
 
                 for(i = 0; (i < 8) ; i++) {
 			status = smbus_read_byte(device, 2);
                         if (status < 0) {
-			         print_debug("bad device: ");
+			         printk(BIOS_DEBUG, "bad device: %d\n", -status);
-				 print_debug_hex8(-status);
-				 print_debug("\n");
 			         break;
 			}
-			print_debug_hex8(status);
+			printk(BIOS_DEBUG, "%02x ", status);
-			print_debug_char(' ');
 		}
 		device++;
-		print_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }

src/mainboard/intel/eagleheights/romstage.c

@@ -20,14 +20,16 @@
  * MA 02110-1301 USA
  */
 
-#include <delay.h>
 #include <stdint.h>
-#include <arch/io.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
+#include <delay.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/speedstep.h>
 #include "southbridge/intel/i3100/early_smbus.c"

src/mainboard/iwill/dk8_htx/romstage.c

@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         setup_mb_resource_map();
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 	setup_coherent_ht_domain(); // routing table and start other core0
 
@@ -115,7 +115,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
-               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+               	printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
 
@@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 

src/mainboard/iwill/dk8s2/romstage.c

@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         setup_default_resource_map();
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 	setup_coherent_ht_domain(); // routing table and start other core0
 
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
-               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+               	printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
 
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 

src/mainboard/iwill/dk8x/romstage.c

@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         setup_default_resource_map();
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 	setup_coherent_ht_domain(); // routing table and start other core0
 
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
-               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+               	printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
 
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 

src/mainboard/jetway/pa78vm5/romstage.c

@@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/kontron/kt690/romstage.c

@@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/lippert/frontrunner/romstage.c

@@ -52,9 +52,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #if CONFIG_DEBUG_SMBUS
 	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
-		print_err("ERROR: spd_read_byte(DIMM0, 0x");
+		printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
-		print_err_hex8(address);
+			"returns 0xff\n", address);
-		print_err(") returns 0xff\n");
 	}
 #endif
 
@@ -85,29 +84,29 @@ void main(unsigned long bist)
 	console_init();
 
 	cs5535_early_setup();
-	print_err("done cs5535 early\n");
+	printk(BIOS_ERR, "done cs5535 early\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
 	pll_reset();
-	print_err("done pll_reset\n");
+	printk(BIOS_ERR, "done pll_reset\n");
 
 	cpuRegInit();
-	print_err("done cpuRegInit\n");
+	printk(BIOS_ERR, "done cpuRegInit\n");
 
 	sdram_initialize(1, memctrl);
 
-	print_err("Done sdram_initialize\n");
+	printk(BIOS_ERR, "Done sdram_initialize\n");
-	print_err("Disable watchdog\n");
+	printk(BIOS_ERR, "Disable watchdog\n");
 	outb( 0x87, 0x4E);                            //enter SuperIO configuration mode
 	outb( 0x87, 0x4E);
 
    	outb(0x20, 0x4e);
 	temp = inb(0x4f);
-	print_debug_hex8(temp);
+	printk(BIOS_DEBUG, "%02x", temp);
 	if (temp != 0x52){
-		print_err("CAN NOT READ SUPERIO VID\n");
+		printk(BIOS_ERR, "CAN NOT READ SUPERIO VID\n");
 	}
 
 	outb(0x29, 0x4e);
@@ -121,9 +120,9 @@ void main(unsigned long bist)
 	outb( 0xC7, 0x4F);
 	outb( 0xF1, 0x4E);                            //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
 	temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
-	print_debug_hex8(temp);print_debug(":");
+	printk(BIOS_DEBUG, "%02x:", temp);
 	temp = temp & ~8;
 	outb( temp, 0x4F);
 	temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
-	print_debug_hex8(temp);print_debug("\n");
+	printk(BIOS_DEBUG, "%02x\n", temp);
 }

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -141,9 +141,7 @@ void main(unsigned long bist)
 	int err;
 	/* bit0 = Spread Spectrum */
 	if ((err = smc_send_config(SMC_CONFIG))) {
-		print_err("ERROR ");
+		printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
-		print_err_char('0'+err);
-		print_err(" sending config data to SMC\n");
 	}
 #endif
 

src/mainboard/lippert/literunner-lx/romstage.c

@@ -84,11 +84,9 @@ int spd_read_byte(unsigned int device, unsigned int address)
 		return 0xFF;	/* No DIMM1, don't even try. */
 
 #if CONFIG_DEBUG_SMBUS
-	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
+	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF)
-		print_err("ERROR: spd_read_byte(DIMM0, 0x");
+		printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
-		print_err_hex8(address);
+			"returns 0xff\n", address);
-		print_err(") returns 0xff\n");
-	}
 #endif
 
 	/* Fake SPD ROM value */
@@ -182,9 +180,7 @@ void main(unsigned long bist)
 
 	/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
 	if ((err = smc_send_config(SMC_CONFIG))) {
-		print_err("ERROR ");
+		printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
-		print_err_char('0'+err);
-		print_err(" sending config data to SMC\n");
 	}
 
 	sdram_initialize(1, memctrl);

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -85,9 +85,8 @@ int spd_read_byte(unsigned int device, unsigned int address)
 
 #if CONFIG_DEBUG_SMBUS
 	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
-		print_err("ERROR: spd_read_byte(DIMM0, 0x");
+		printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
-		print_err_hex8(address);
+			"returns 0xff\n", address);
-		print_err(") returns 0xff\n");
 	}
 #endif
 
@@ -179,9 +178,7 @@ void main(unsigned long bist)
 
 	/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
 	if ((err = smc_send_config(SMC_CONFIG))) {
-		print_err("ERROR ");
+		printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
-		print_err_char('0'+err);
-		print_err(" sending config data to SMC\n");
 	}
 
 	sdram_initialize(1, memctrl);

src/mainboard/msi/ms7135/romstage.c

@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= ht_setup_chains_x();
 	needs_reset |= ck804_early_setup_x();
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/msi/ms7260/romstage.c

@@ -131,9 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	report_bist_failure(bist); /* Halt upon BIST failure. */
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-	print_debug("bsp_apicid=");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-	print_debug_hex8(bsp_apicid);
-	print_debug("\n");
 
 	/* In BSP so could hold all AP until sysinfo is in RAM. */
 	set_sysinfo_in_ram(0);
@@ -158,20 +156,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if CONFIG_SET_FIDVID
 	{
 		msr_t msr = rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid ");
+		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-		print_debug_hex32(msr.hi);
-		print_debug_hex32(msr.lo);
-		print_debug("\n");
 	}
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 	init_fidvid_bsp(bsp_apicid);
 	{
 		msr_t msr = rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid ");
+		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-		print_debug_hex32(msr.hi);
-		print_debug_hex32(msr.lo);
-		print_debug("\n");
 	}
 #endif
 
@@ -183,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 	allow_all_aps_stop(bsp_apicid);

src/mainboard/msi/ms9185/romstage.c

@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device(PCI_DEV(0, 0x19, 0));
 #endif
 
-       print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+       printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
        setup_coherent_ht_domain();
 
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
         enable_fid_change();
         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+                printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 #endif
 
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
                 soft_reset();
         }
 #endif

src/mainboard/msi/ms9282/romstage.c

@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	needs_reset |= mcp55_early_setup_x();
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/newisys/khepri/romstage.c

@@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	report_bist_failure(bist);
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 	setup_coherent_ht_domain(); // routing table and start other core0
@@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 #endif
 
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 	      	soft_reset();
 	}
 	allow_all_aps_stop(bsp_apicid);

src/mainboard/pcengines/alix1c/romstage.c

@@ -83,19 +83,15 @@ static const u8 spdbytes[] = {
 
 int spd_read_byte(unsigned int device, unsigned int address)
 {
-	print_debug("spd_read_byte dev ");
+	printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);
-	print_debug_hex8(device);
 
 	if (device != DIMM0) {
-		print_debug(" returns 0xff\n");
+		printk(BIOS_DEBUG, " returns 0xff\n");
 		return 0xff;
 	}
 
-	print_debug(" addr ");
+	printk(BIOS_DEBUG, " addr %02x returns %02x\n",
-	print_debug_hex8(address);
+		address, spdbytes[address]);
-	print_debug(" returns ");
-	print_debug_hex8(spdbytes[address]);
-	print_debug("\n");
 
 	return spdbytes[address];
 }
@@ -156,9 +152,9 @@ void main(unsigned long bist)
 	 * We use method 1 on Norwich and on this board too.
 	 */
 	post_code(0x02);
-	print_err("POST 02\n");
+	printk(BIOS_ERR, "POST 02\n");
 	__asm__("wbinvd\n");
-	print_err("Past wbinvd\n");
+	printk(BIOS_ERR, "Past wbinvd\n");
 
 	/* We are finding the return does not work on this board. Explicitly
 	 * call the label that is after the call to us. This is gross, but

src/mainboard/pcengines/alix2d/romstage.c

@@ -81,19 +81,15 @@ static const u8 spdbytes[] = {
 
 int spd_read_byte(unsigned int device, unsigned int address)
 {
-	print_debug("spd_read_byte dev ");
+	printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);
-	print_debug_hex8(device);
 
 	if (device != DIMM0) {
-		print_debug(" returns 0xff\n");
+		printk(BIOS_DEBUG, " returns 0xff\n");
 		return 0xff;
 	}
 
-	print_debug(" addr ");
+	printk(BIOS_DEBUG, " addr %02x returns %02x\n",
-	print_debug_hex8(address);
+		address, spdbytes[address]);
-	print_debug(" returns ");
-	print_debug_hex8(spdbytes[address]);
-	print_debug("\n");
 
 	return spdbytes[address];
 }
@@ -179,9 +175,9 @@ void main(unsigned long bist)
 	 * We use method 1 on Norwich and on this board too.
 	 */
 	post_code(0x02);
-	print_err("POST 02\n");
+	printk(BIOS_ERR, "POST 02\n");
 	__asm__("wbinvd\n");
-	print_err("Past wbinvd\n");
+	printk(BIOS_ERR, "Past wbinvd\n");
 
 	/* We are finding the return does not work on this board. Explicitly
 	 * call the label that is after the call to us. This is gross, but

src/mainboard/sunw/ultra40/romstage.c

@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
         needs_reset |= ck804_early_setup_x();
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -146,9 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	setup_mb_resource_map();
 
-	print_debug("bsp_apicid=");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-	print_debug_hex8(bsp_apicid);
-	print_debug("\n");
 
 	set_sysinfo_in_ram(0);	// in BSP so could hold all ap until sysinfo is in ram
 #if CONFIG_DEBUG_SMBUS
@@ -174,10 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr = rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid ");
+		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-		print_debug_hex32(msr.hi);
-		print_debug_hex32(msr.lo);
-		print_debug("\n");
 	}
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -186,10 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr = rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid ");
+		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-		print_debug_hex32(msr.hi);
-		print_debug_hex32(msr.lo);
-		print_debug("\n");
 	}
 #endif
 
@@ -201,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         setup_mb_resource_map();
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+        printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
         setup_coherent_ht_domain(); // routing table and start other core0
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\n");
+                printk(BIOS_INFO, "ht reset -\n");
               	soft_reset();
         }
 

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/supermicro/h8qgi/romstage.c

@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3D);
 	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		distinguish_cpu_resets(0);
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -107,14 +107,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x42);
 
 	post_code(0x50);
-	print_debug("Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as ram ");
 	disable_cache_as_ram();
-	print_debug("done\n");
+	printk(BIOS_DEBUG, "done\n");
 
 	post_code(0x51);
 	copy_and_run();
 
 	/* We will not return,  Should never see this message and post code. */
-	print_debug("should not be here -\n");
+	printk(BIOS_DEBUG, "should not be here -\n");
 	post_code(0x54);
 }

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -269,7 +269,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
  if (!warm_reset_detect(0)) {
-   print_info("...WARM RESET...\n\n\n");
+   printk(BIOS_INFO, "...WARM RESET...\n\n\n");
               	soft_reset();
    die("After soft_reset_x - shouldn't see this message!!!\n");
         }

src/mainboard/supermicro/h8scm/romstage.c

@@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3D);
 	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		distinguish_cpu_resets(0);
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -101,14 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x42);
 
 	post_code(0x50);
-	print_debug("Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as ram ");
 	disable_cache_as_ram();
-	print_debug("done\n");
+	printk(BIOS_DEBUG, "done\n");
 
 	post_code(0x51);
 	copy_and_run();
 
 	/* We will not return,  Should never see this message and post code. */
-	print_debug("should not be here -\n");
+	printk(BIOS_DEBUG, "should not be here -\n");
 	post_code(0x54);
 }

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -196,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/technexion/tim5690/romstage.c

@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/technexion/tim8690/romstage.c

@@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 

src/mainboard/tyan/s2850/romstage.c

@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s2875/romstage.c

@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s2880/romstage.c

@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s2881/romstage.c

@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s2882/romstage.c

@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s2885/romstage.c

@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s2912/romstage.c

@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 	setup_coherent_ht_domain(); // routing table and start other core0
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 	}
 #endif
 
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 	      	soft_reset();
 	}
 

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}

src/mainboard/tyan/s4880/romstage.c

@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s4882/romstage.c

@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\n");
+               	printk(BIOS_INFO, "ht reset -\n");
                	soft_reset();
        	}
 

src/mainboard/tyan/s8226/romstage.c

@@ -96,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3D);
 	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
 	if (!warm_reset_detect(0)) {
-		print_info("...WARM RESET...\n\n\n");
+		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 		distinguish_cpu_resets(0);
 		soft_reset();
 		die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -110,14 +110,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x42);
 
 	post_code(0x50);
-	print_debug("Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as ram ");
 	disable_cache_as_ram();
-	print_debug("done\n");
+	printk(BIOS_DEBUG, "done\n");
 
 	post_code(0x51);
 	copy_and_run();
 
 	/* We will not return,  Should never see this message and post code. */
-	print_debug("should not be here -\n");
+	printk(BIOS_DEBUG, "should not be here -\n");
 	post_code(0x54);
 }

src/mainboard/via/epia-m700/romstage.c

@@ -57,7 +57,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
 	device_t dev;
 	u16 tmp, result;
 
-	print_debug("In acpi_is_wakeup_early_via_vx800\n");
+	printk(BIOS_DEBUG, "In acpi_is_wakeup_early_via_vx800\n");
 	/* Power management controller */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				       PCI_DEVICE_ID_VIA_VX855_LPC), 0);
@@ -73,9 +73,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
 
 	tmp = inw(VX800_ACPI_IO_BASE + 0x04);
 	result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
-	print_debug("         boot_mode=");
+	printk(BIOS_DEBUG, "         boot_mode=%04x\n", result);
-	print_debug_hex16(result);
-	print_debug("\n");
 	return result;
 }
 
@@ -116,7 +114,7 @@ static void enable_mainboard_devices(void)
 	pci_write_config8(dev, 0x5b, 0x01);
 #endif
 
-	print_debug("In enable_mainboard_devices\n");
+	printk(BIOS_DEBUG, "In enable_mainboard_devices\n");
 
 	/* Enable P2P Bridge Header for external PCI bus. */
 	dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
@@ -451,7 +449,7 @@ void main(unsigned long bist)
 	/* Halt if there was a built-in self test failure. */
 	report_bist_failure(bist);
 
-	print_debug("Enabling mainboard devices\n");
+	printk(BIOS_DEBUG, "Enabling mainboard devices\n");
 	enable_mainboard_devices();
 
 	/*
@@ -460,9 +458,7 @@ void main(unsigned long bist)
 	 */
 	device = PCI_DEV(0, 0, 4);
 	Data = pci_read_config8(device, 0xf6);
-	print_debug("NB chip revision =");
+	printk(BIOS_DEBUG, "NB chip revision = %02x\n", Data);
-	print_debug_hex8(Data);
-	print_debug("\n");
 
 	/* Make NB ready before DRAM init. */
 	via_pci_inittable(Data, mNbStage1InitTbl);
@@ -479,7 +475,7 @@ void main(unsigned long bist)
 		u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
 		DRAM_SYS_ATTR DramAttr;
 
-		print_debug("This is an S3 wakeup\n");
+		printk(BIOS_DEBUG, "This is an S3 wakeup\n");
 
 		memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
 		/*
@@ -514,7 +510,7 @@ void main(unsigned long bist)
 		/* Just copy this function from draminit to here! */
 		SetUMARam();
 
-		print_debug("Resume from S3, RAM init was ignored\n");
+		printk(BIOS_DEBUG, "Resume from S3, RAM init was ignored\n");
 	} else {
 		ddr2_ram_setup();
 		ram_check(0, 640 * 1024);
@@ -634,7 +630,7 @@ void main(unsigned long bist)
 		);
 #endif
 		/* This can have function call, because no variable used before this. */
-		print_debug("Copy memory to high memory to protect s3 wakeup vector code\n");
+		printk(BIOS_DEBUG, "Copy memory to high memory to protect s3 wakeup vector code\n");
 		memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
 				 0x100000), (unsigned char *)0, 0xa0000);
 		memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -

src/mainboard/via/epia-m850/mainboard.c

@@ -100,7 +100,7 @@ static void mainboard_enable(device_t dev)
 	(void)dev;
 
 #if CONFIG_VGA_ROM_RUN
-	print_debug("Installing INT15 handler...\n");
+	printk(BIOS_DEBUG, "Installing INT15 handler...\n");
 	mainboard_interrupt_handlers(0x15, &vx900_int15_handler);
 #endif
 }

src/mainboard/via/epia-m850/romstage.c

@@ -55,7 +55,7 @@ void main(unsigned long bist)
 	/* Serial console is easy to take care of */
 	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	print_debug("Console initialized.\n");
+	printk(BIOS_DEBUG, "Console initialized.\n");
 
 	vx900_cpu_bus_interface_setup();
 
@@ -91,7 +91,7 @@ void main(unsigned long bist)
 	if (tolm > (2 * (u32) GiB))
 		ram_check(2048 << 20, 0x80);
 
-	print_debug("We passed RAM verify\n");
+	printk(BIOS_DEBUG, "We passed RAM verify\n");
 
 	/* We got RAM working, now we can write the timestamps to RAM */
 #if CONFIG_EARLY_CBMEM_INIT

src/mainboard/wyse/s50/romstage.c

@@ -70,10 +70,10 @@ void main(unsigned long bist)
 	pll_reset();
 
 	cpuRegInit();
-	print_err("done cpuRegInit\n");
+	printk(BIOS_ERR, "done cpuRegInit\n");
 
 	sdram_initialize(1, memctrl);
-	print_err("ram setup done\n");
+	printk(BIOS_ERR, "ram setup done\n");
 
 	msr_init();
 }