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mb/intel/tglrvp: Add DTT support for tglrvp 

Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board.
Set power limits and CPU sensor thresholds for DTT based thermal control.

BRANCH=None
BUG=None
TEST=Build and boot on tglrvp board

Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Sumeet R Pawnikar 2020-09-09 23:44:06 +05:30 committed by Patrick Georgi
parent 27dc761d08
commit 06b35e5ced
3 changed files with 84 additions and 2 deletions
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2
src/mainboard/intel/tglrvp/Kconfig
View File

@ -7,12 +7,14 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select DRIVERS_I2C_HID
select DRIVERS_INTEL_DPTF
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_MAX98373
select DRIVERS_INTEL_PMC
select DRIVERS_USB_ACPI
select DRIVERS_SPI_ACPI
select SOC_INTEL_TIGERLAKE
select SOC_INTEL_COMMON_BLOCK_DTT
select INTEL_LPSS_UART_FOR_CONSOLE
select DRIVERS_INTEL_ISH
select EC_ACPI

42
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -121,6 +121,24 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"
# Enable Processor Thermal Control
register "Device4Enable" = "1"
# Add PL1 and PL2 values
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 38,
.tdp_pl4 = 71,
}"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 60,
.tdp_pl4 = 105,
}"
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
@ -155,7 +173,29 @@ chip soc/intel/tigerlake
#From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
device pci 02.0 on end # Graphics
device pci 04.0 on end # DPTF 0x9A03
device pci 04.0 on
# Default DPTF Policy for all tglrvp_up3 boards if not overridden
chip drivers/intel/dptf
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
# Power Limits Control
register "controls.power_limits.pl1" = "{
.min_power = 3000,
.max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 15000,
.max_power = 60000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"
device generic 0 on end
end
end # DPTF 0x9A04:U22/0x9A14:U42
device pci 05.0 on end # IPU 0x9A19
device pci 06.0 on end # PEG60 0x9A09
device pci 07.0 on end # TBT_PCIe0 0x9A23

42
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -115,6 +115,24 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"
# Enable Processor Thermal Control
register "Device4Enable" = "1"
# Add PL1 and PL2 values
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 9,
.tdp_pl2_override = 35,
.tdp_pl4 = 66,
}"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 9,
.tdp_pl2_override = 40,
.tdp_pl4 = 83,
}"
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
@ -149,7 +167,29 @@ chip soc/intel/tigerlake
#From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
device pci 02.0 on end # Graphics
device pci 04.0 on end # DPTF 0x9A03
device pci 04.0 on
# Default DPTF Policy for all tglrvp_up4 boards if not overridden
chip drivers/intel/dptf
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
# Power Limits Control
register "controls.power_limits.pl1" = "{
.min_power = 3000,
.max_power = 9000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 9000,
.max_power = 40000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"
device generic 0 on end
end
end # DPTF 0x9A02:Y22/0x9A12:Y42
device pci 05.0 on end # IPU 0x9A19
device pci 06.0 on end # PEG60 0x9A09
device pci 07.0 on end # TBT_PCIe0 0x9A23